參數(shù)資料
型號(hào): VPX3224E
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Video Pixel Decoders
中文描述: 視頻解碼器像素
文件頁(yè)數(shù): 73/92頁(yè)
文件大?。?/td> 616K
代理商: VPX3224E
ADVANCE INFORMATION
VPX 322xE
MICRONAS INTERMETALL
73
Table 6–3:
I
2
C-Registers VPX Slicer
I
2
C-Registers VPX Slicer
Address
Hex
Number
of bits
Mode
Function
Default
Name
Sync Slicer (of Data Slicer only)
h’C8
8
w
sync slicer
bit[6:0] :
binary sync slicer level is compared with binary data
(0
data
127)
0
vertical sync window enable
1
vertical sync window disable
bit[7] :
64
0
sync_slicer
sync_level
vsw
h’B4
8
r
sync status
bit[5:0] :
bit[6] :
reserved (must be read don’t care)
0
vert. window
1
vert. retrace
0
field 2
1
field 1
reset at line 624/524 (PAL/NTSC)
set at line 628/528 (PAL/NTSC)
reset at line 313/263 (PAL/NTSC)
set at line 624/524 (PAL/NTSC)
bit[7] :
sync_stat
vwin
field
h’B5
8
r
hsync counter
bit[7:0] :
number of detected horizontal sync pulses per frame / 4
sync is detected within horizontal window of HPLL
counter is latched with vertical sync
the register can be read at any time
sync_cnt
Bit Slicer
h’C0
8
w
soft slicer
bit[6:0] :
binary soft slicer level is compared with ABS[data]
(–128
data
+127)
reserved (must be set to zero)
bit[7] :
16
soft_slicer
soft_level
h’C1
h’C2
8
8
w
w
ttx bitslicer frequency LSB
ttx bitslicer frequency MSB
bit[10:0] :Freq
= 2
11
* bitfreq / 20.25MHz
= 702 for WST PAL
= 579 for WST NTSC or NABTS
= 506 for VPS or WSS
= 102 for CAPTION
= 627 for Antiope
= 183 for Time Code
phase inc = Freq
phase inc = Freq*(1+1/8) before framing code
phase inc = Freq*(1+1/16) after framing code
bit[15:12] : reserved (must be set to zero)
bit[11] :
0
1
702
1
0
ttx_freql
ttx_freqh
ttx_freq
ttx_phinc
h’C5
8
w
filter coefficient
bit[5:0] :
high pass filter coefficient in 2’s complement
not allowed
bit[7:6] :
reserved (must be set to zero)
7
filter
coeff
h’C6
8
w
data slicer
bit[7:0] :
binary data slicer level is compared with ABS[data]
(–128
data
+127)
64
data_slicer
data_level
相關(guān)PDF資料
PDF描述
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