參數(shù)資料
型號: WEDPNF8M722V-XBX
英文描述: 8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module(8Mx72同步動(dòng)態(tài)RAM+16M位閃速存儲(chǔ)器混合型模塊)
中文描述: 8Mx72同步DRAM 16Mb的閃存混合模塊(8Mx72同步動(dòng)態(tài)RAM的1,600位閃速存儲(chǔ)器混合型模塊)
文件頁數(shù): 11/41頁
文件大小: 522K
代理商: WEDPNF8M722V-XBX
11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M722V-XBX
TABLE 3 TRUTH TABLE - COMMANDS AND DQM OPERATION
(Note 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
Write Enable/Output Enable (8)
Write Inhibit/Output High-Z (8)
NOTES:
1.CKE is HIGH for all commands shown except SELF REFRESH.
2.A
0-11
define the op-code written to the Mode Register.
3.A
0-11
provide row address, and BA
0
, BA
1
determine which bank is made active.
4.A
0-8
provide column address; A
10
HIGH enables the auto precharge feature (nonpersistent), while A
10
LOW disables the auto precharge feature; BA
0
, BA
1
determine which bank is being read from or written to.
5.A
10
LOW: BA
0
, BA
1
determine the bank being precharged. A
10
HIGH: All banks precharged and BA
0
, BA
1
are “Don’t Care.”
6.This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7.Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8.Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay).
CS
H
L
L
L
L
L
L
L
L
RAS
X
H
L
H
H
H
L
L
L
CAS
X
H
H
L
L
H
H
L
L
WE
X
H
H
H
L
L
L
H
L
DQM
X
X
X
L/H
8
L/H
8
X
X
X
X
L
H
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
I/Os
X
X
X
X
Valid
Active
X
X
X
Active
High-Z
READ
The READ command is used to initiate a burst read access to an
active row. The value on the BA
0
, BA
1
inputs selects the bank, and
the address provided on inputs A
0-8
selects the starting column
location. The value on input A
10
determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row
being accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain open for
subsequent accesses. Read data appears on the I/Os subject to the
logic level on the DQM inputs two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding I/Os will be High-Z two
clocks later; if the DQM signal was registered LOW, the I/Os will
provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an
active row. The value on the BA
0
, BA
1
inputs selects the bank, and
the address provided on inputs A
0-8
selects the starting column
location. The value on input A
10
determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for subsequent
accesses. Input data appearing on the I/Os is written to the memory
array subject to the DQM input logic level appearing coincident with
the data. If a given DQM signal is registered LOW, the corresponding
data will be written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from
being executed by the SDRAM, regardless of whether the CLK
signal is enabled. The SDRAM is effectively deselected. Opera-
tions already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to
an SDRAM which is selected (CS is LOW). This prevents unwanted
commands from being registered during idle or wait states. Op-
erations already in progress are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A
0-11
. See Mode Register
heading in the Register Definition section. The LOAD MODE
REGISTER command can only be issued when all banks are idle,
and a subsequent executable command cannot be issued until
t
MRD
is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a
particular bank for a subsequent access. The value on the BA
0
,
BA
1
inputs selects the bank, and the address provided on inputs
A
0-11
selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a different
row in the same bank.
相關(guān)PDF資料
PDF描述
WEDPS512K32V-XBX SRAM MCP
WEDPS512K32-XBX SRAM MCP
WEDPY256K72V-XBX SSRAM MCP
WEDPZ512K72S-XBX NBL SSRAM MCP
WEDPZ512K72V-XBX NBL SSRAM MCP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
WEDPS512K32-12BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx32 SRAM MULTI-CHIP PACKAGE
WEDPS512K32-12BI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx32 SRAM MULTI-CHIP PACKAGE
WEDPS512K32-12BM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx32 SRAM MULTI-CHIP PACKAGE
WEDPS512K32-15BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx32 SRAM MULTI-CHIP PACKAGE
WEDPS512K32-15BI 制造商:White Electronic Designs 功能描述:SRAM Module Asynchronous 16Mbit