參數(shù)資料
型號(hào)： WEDPNF8M722V-XBX
英文描述： 8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module(8Mx72同步動(dòng)態(tài)RAM+16M位閃速存儲(chǔ)器混合型模塊)
中文描述： 8Mx72同步DRAM 16Mb的閃存混合模塊（8Mx72同步動(dòng)態(tài)RAM的1,600位閃速存儲(chǔ)器混合型模塊）
文件頁(yè)數(shù)： 17/41頁(yè)
文件大?。?/td> 522K
代理商： WEDPNF8M722V-XBX
17
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M722V-XBX
STANDBY MODE
When the system is not reading or writing to the device, it can
place the device in standby mode. In this mode, current consump-
tion is greatly reduced, and the outputs are placed in the high
impedance state, independent of the FOE input.
The device enters the CMOS standby mode when the FCS1-2 and
RST pins are held at Vcc
±
0.3V. (Note that this is a more restricted
voltage range than V
IH
.) If FCS1-2 and RST are held at V
IH
, but not
within Vcc
±
0.3V the device will be in the standby mode, but the
standby current will be greater. The device requires standard
access time (t
CE
) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
In the Flash DC Characteristics table, I
FCC3
and I
FCC4
represent the
standby current specifications.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode when
addresses remain stable for t
+ 30 ns. The automatic sleep
mode is independent of the FCS1-2, FWE, and FOE control signals.
Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and
always available to the system. IFcc
in the DC Characteristics
table represents the automatic sleep mode current specification.
RST: HARDWARE RESET PIN
The RST pin provides a hardware method of resetting the device
to reading array data. When the RST pin is driven low for at least
a period of t
RP
or greater the device immediately terminates any
operation in progress, tristates all output pins, and ignores all
read/write commands for the duration of the RST pulse. The
device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated
once the device is ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RST pulse. When RST is
held at Vss
±
0.3V, the device draws CMOS standby current (I
FCC4
).
If RST is held at V
IL
but not within Vss
±
0.3V, the standby current
will be greater.
The RST pin may be tied to the system reset circuitry. A system
reset would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory.
If RST is asserted during a program or erase operation, RY/BY1 pin
remains “0” (busy) until the internal reset operation is complete,
which requires a time of t
READY
(during Embedded Algorithms).
The system can thus monitor RY/BY1-2 to determine whether the
reset operation is complete. If RST is asserted when a program or
erase operation is not executing (RY/BY1-2 pins are “1”), the reset
operation is completed within a time of t
READY
(not during Embed-
ded Algorithms). The system can read data t
RH
after the RST pin
returns to V
IH
.
Refer to the Flash AC Characteristics and hardware reset tables
for RST parameters and to Figure 19 for the timing diagram.
TABLE 5 - BOTTOM BOOT BLOCK SECTOR ADDRESS TABLE
Sector Size
(Kbytes)
16
8
8
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
(x8) Address Range
(In hexidecimal)
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-FFFFFh
Sector
SA
0
SA
1
SA
2
SA
3
SA
4
SA
5
SA
6
SA
7
SA
8
SA
9
SA
10
SA
11
SA
12
SA
13
SA
14
SA
15
SA
16
SA
17
SA
18
A
18
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A
17
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
16
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
15
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
14
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
13
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
12
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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