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| 型號： | WEDPNF8M722V-XBX |
| 英文描述： | 8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module(8Mx72同步動態(tài)RAM+16M位閃速存儲器混合型模塊) |
| 中文描述： | 8Mx72同步DRAM 16Mb的閃存混合模塊（8Mx72同步動態(tài)RAM的1,600位閃速存儲器混合型模塊） |
| 文件頁數(shù)： | 25/41頁 |
| 文件大小： | 522K |
| 代理商： | WEDPNF8M722V-XBX |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M722V-XBX
RY/BY1-2: Ready/Busy
The RY/BY1-2 is a dedicated, open drain output pin that indicates
whether an Embedded Algorithm is in progress or complete. The
RY/BY1-2 status is valid after the rising edge of the final FWE
pulse in the command sequence.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase Suspend
mode.) If the output is high (Ready), the device is ready to read
array data (including during the Erase Suspend mode.), or is in the
standby mode.
Table 8 shows the outputs for RY/BY1-2. Figures
11, 12, 13, 19
show
RY/BY1-2 for read, program, erase and reset operations, respectively.
FD6/FD22: Toggle Bit I
“Toggle Bit I” on FD
6
/FD
22
indicates whether an Embedded Program
or Erase Algorithm is in progress or has been completed, or
whether the device has entered the Erase Suspend mode. Toggle
Bit I may read at any address, and is valid after the rising edge of
the final FWE pulse in the command sequence (prior to the
program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase Algorithm operation,
successive read cycles to any address will result in FD
6
/FD
22
toggling. (The system may use either FOE or FCS1-2 to control the
read cycles.) When operation is complete, FD
6
/FD
22
stop toggling.
After the erase command sequence is written, if all sectors
selected for erasing are protected, FD
6
/FD
22
toggles for approximately
100
μ
s, then returns to reading array data. If not all selected
sectors are protected, the Embedded Erase Algorithm erases the
unprotected sectors, and ignores the selected sectors that are
protected.
The system can use FD
6
/FD
22
and FD
2/
FD
18
respectively
,
together
to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the
Embedded Erase Algorithm is in progress) FD
6
/FD
22
toggles.
When the device enters the Erase Suspend mode, FD
6
/FD
22
stops
toggling. However, the system must also use FD
2
/FD
18
to determine
which sectors are erasing or erase-suspended. Alternatively, the
system can use FD
7
/FD
23
(see the subsection on “FD
7
/FD
23
: Data
Polling”).
If a program address falls within a protected sector, FD
6
/FD
22
also
toggles for approximately 1
μ
s after the program command sequence
is written, then returns to reading array data.
FD
6
/FD
22
also toggles during erase-suspend-program mode, and
stops toggling once the Embedded Program algorithm is complete.
Table 8 shows the outputs for “Toggle Bit I” on FD
6
/FD
22
. Figure
9 shows the Toggle Bit Algorithm. Figure 20 shows the toggle bit
timing diagrams. Figure 19 shows the difference between FD
2
/
FD
18
and FD
6
/FD
22
in graphical form. See also the subsection on
“FD
2
/FD
18
: Toggle Bit II”.
FD
2
: Toggle Bit II
The “Toggle Bit II” on FD
2
/FD
18
, when used with FD
6
/FD
22
, indicates
whether a particular sector is actively erasing (that is, the Embedded
Erase Algorithm is in progress) or whether that sector is erase-
suspended. “Toggle Bit II” is valid after the rising edge of the final
FWE pulse in the command sequence.
FD
2
/FD
18
toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The system
may use either FOE or FCS
1-2
to control the read cycles.) FD
2
/FD
18
cannot distinguish whether the sector is actively erasing or is
erase-suspended. FD
6
/FD
22
, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to
Table 8 to compare outputs for FD
2
/FD
18
and FD
6
/FD
22
.
Figure 8 shows the Toggle Bit Algorithm in flowchart form, and the
section “FD
2
/FD
18
: Toggle Bit II” explains the algorithm. See also
the subsection on “FD
6
/FD
22
: Toggle Bit I”. Figure 20 shows the
toggle bit timing diagrams. Figure 19 shows the difference between
FD
2
/FD
18
and FD
6
/FD
22
in graphical form.
Reading Toggle Bits FD
6,22
/FD
2,18
Refer to Figure 8 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read FD
7-
FD
0,
and FD
23
-FD
16
respectively, at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system would note
and store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The system can
read array data on FD
7-0,
and FD
23
-FD
16
respectively, on the
following read cycle.
However, if after the initial two read cycles, the system determines
that the toggle bit is still toggling, the system also should note
whether the value of FD
5
/FD
21
is high (see the section on FD
5
/
FD
21
). If it is, the system should then determine again whether the
toggle bit is toggling, since the toggle bit may have stopped
toggling just as the device has successfully completed the program
or erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that
the toggle bit is toggling and FD
5
/FD
21
has not gone high. The
system may continue to monitor the toggle bit and FD
5
/FD
21
through successive read cycles, determining the status as described
in the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine the status
of the operation (top of Figure 8).
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