參數(shù)資料
型號(hào)： WEDPNF8M722V-XBX
英文描述： 8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module(8Mx72同步動(dòng)態(tài)RAM+16M位閃速存儲(chǔ)器混合型模塊)
中文描述： 8Mx72同步DRAM 16Mb的閃存混合模塊（8Mx72同步動(dòng)態(tài)RAM的1,600位閃速存儲(chǔ)器混合型模塊）
文件頁(yè)數(shù)： 23/41頁(yè)
文件大?。?/td> 522K
代理商： WEDPNF8M722V-XBX
23
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M722V-XBX
LEGEND:
X = Don't Care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the FWE or FCS1-2 pulses, whichever occurs first.
PD = Data to be programmed at location PA. Data is latched on the rising edge of FWE or FCS1-2 pulses, whichever occurs first.
SA = Address of the sector to be erased. The combination of FA
18
-
12
will uniquely select any sector.
NOTES:
1. Bus operations are defined in Table 3.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Address bits FA
18
-
11
= don’t care for unlock and command cycles, unless PA or SA is required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if FD
5
and FD
21
, respectively goes high (while the device is
providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector.
9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10.The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode.
11.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only
during a sector erase operation.
12.The Erase Resume command is valid only during the Erase Suspend mode.
13.Data bits FD
8-15
and FD
24-31,
respectively are don’t cares for unlock and command cycles.
14.The Command Definitions refer to each Flash device individually.
TABLE 7 - COMMAND DEFINITIONS (14)
Bus Cycles (Notes 2, 3, 4, 13)
First Bus
Cycle
Second Bus
Cycle
Third Bus
Cycle
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Addr
RA
Data
RD
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (Note 5)
1
Reset (Note 6)
Device ID,
Bottom Boot Block
A
1
XXX
F0
Byte
Word
Byte
4
AAA
555
AAA
AA
555
2AA
555
55
AAA
555
AAA
90
X02
X01
(SA)
X04
(SA)
X02
5B
225B
XX00
01
XX00
XX01
4
AA
55
90
Word
555
2AA
555
Program
Byte
Word
Byte
Word
4
AAA
555
AAA
555
XXX
AA
555
2AA
555
2AA
PA
55
AAA
555
AAA
555
A0
PA
PD
Unlock Bypass
3
AA
55
20
Unlock Bypass Program (Note 9)
2
A0
PD
Unlock Bypass Reset (Note10)2
XXX
90
PA
00
Chip Erase
Byte
Word
Byte
Word
6
AAA
555
AAA
555
XXX
AA
555
2AA
555
2AA
55
AAA
555
AAA
555
80
AAA
555
AAA
555
AA
555
2AA
555
2AA
55
AAA
555
10
Sector Erase
6
AA
55
80
AA
55
SA
30
Erase Suspended (Note 11)
1
B0
Erase Resume (Note 12)
1
XXX
30
Bus
Write
Cycles
Req'd
Command
Sequence
(Note 1)
Sector Protect
Verify (Note 7,8)
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