參數(shù)資料
型號(hào)： WEDPNF8M722V-XBX
英文描述： 8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module(8Mx72同步動(dòng)態(tài)RAM+16M位閃速存儲(chǔ)器混合型模塊)
中文描述： 8Mx72同步DRAM 16Mb的閃存混合模塊（8Mx72同步動(dòng)態(tài)RAM的1,600位閃速存儲(chǔ)器混合型模塊）
文件頁(yè)數(shù)： 24/41頁(yè)
文件大小： 522K
代理商： WEDPNF8M722V-XBX
24
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M722V-XBX
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write
operation: FD
2
, FD
3
, FD
5
, FD
6
, and FD
7;
FD
18
, FD
19
, FD
21
, FD
22
and
FD
23
respectively. Table 8 and the following subsections describe
the functions of these bits. FD
7,
RY/BY1, and FD
6
; FD23, RY/BY2,
and FD22 respectively each offer a method for determining whether
a program or erase operation is complete or in progress. These
bits are discussed first.
FD
7/
FD
23
: Data Polling
The Data Polling bit, FD
7
/FD
23
, indicates to the host system
whether an Embedded Algorithm is in progress or completed, or
whether the device is in Erase Suspend Data Polling valid after the
rising edge of the final FWE pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device outputs on
FD
7/
FD
23
the complement of the datum programmed to FD
7/
FD
23
.
This FD
7/
FD
23
status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is complete, the
device outputs the datum programmed to FD
7/
FD
23
. The system
must provide the program address to read valid status information
on FD
7/
FD
23
. If a program address falls within a protected sector,
Data Polling on FD
/
FD
237
is active for approximately 1
μ
s, then the
device returns to reading array data.
During the Embedded Erase algorithm, Data Polling produces a
“0” on FD
7/
FD
23
. When the Embedded Erase algorithm is complete,
or if the device enters the Erase Suspend mode, Data Polling
produces a “1” on FD
7/
FD
23
. This analogous to the complement/
true datum output described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to “1”; prior to
this, the device outputs the “complement,” or “0.” The system
must provide an address within any of the sectors selected for
erasure to read valid status information on FD
7/
FD
23
.
After an erase command sequence is written, if all sectors selected
for erasing are protected, Data Polling on FD
7/
FD
23
is active for
approximately 100
μ
s, then the device returns to reading array
data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected.
When the system detects FD
7/
FD
23
has changed from the complement
to true data, it can read valid data at FD
7-0
and
FD
23-16
respectively
on the following ead cycles. This because FD
7/
FD
23
may change
asynchronously with FD
0-6
and FD
16-22
respectively while Flash
Output Enable (FOE) is asserted low. Figure 14, Data Polling
timings (During Embedded algorithms), in the “Flash AC
characteristics” section illustrates this.
Table 8 shows the outputs for Data Polling on FD
7
/FD
23
. Figure 7
shows the Data Polling algorithm.
FIG.7
DATA POLLING ALGORITHM
1. FD
7
/FD
23
should be rechecked even if FD
5
/FD
21
= 1 because FD
7
/FD
23
may
change simultaneously with FD
5
/FD
21
respectively.
Start
Read Byte
(FD0-7/FD16-23)
Addr = VA
Read Byte
(FD0-7-FD16-23)
Addr = VA
Fail
FD7/FD23 = Data
FD5/FD21 = 1
FD7/FD23 = Data
No
Yes
Yes
Yes
No
Pass
No
VA = Byte address for programming
= Any of the sector addresses within the
sector being erased during sector erase
operation
= Valid address equals any non-protected
sector group address during chip erase
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