Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
10
CONTROL REGISTER OVERVIEW
There are two types of control registers in the XA-H4, these are SFRs
(Special Function Registers), and MMRs (Memory Mapped Registers.)
The SFR registers, with the exception of MRBL, MRBH, MICFG, BCR,
BRTH, BRTL, and RSTSRC are the standard XA core registers. See
WARNINGs
about BCR, BRTH, and BRTL in Table 2.
SFRs are accessed by “direct addressing” only (see IC25 XA User
Manualfor direct addressing.) The MMRs are specific to the XA-H4
on-chip peripherals, and can be accessed by any addressing mode
that can be used for off-chip data accesses. The MMRs are
implemented in a relocatable block. See the “Memory Controller”
chapter in the XA-H4 User Manualfor details on how to relocate the
MMRs by writing a new base address into the MRBL and MRBH
(MMR Base Low and High) registers.
Table 2. Special Function Registers (SFR)
Name
Description
SFR
Address
Bit Functions and Addresses
MSB
WARNING
– Never write to the BCR register in the XA-H4 – it is initialized to 07h,
the only legal value. This is not the same as for some other XA derivatives.
LSB
Reset
Value
BCR
Bus Configuration Reg
RESERVED – see
Warning
46Ah
07h
BTRH
Bus Timing Reg High
469h
WARNING
– Immediately after reset, always write BTRH = 51h, followed by
writing BTRL = 40h in that order Follow these two writes with five NOPS This is
writing BTRL = 40h in that order. Follow these two writes with five NOPS. This is
not the same as for some other XA derivatives.
FFh
BTRL
Bus Timing Reg Low
468h
EFh
MRBL#
MMR Base Address Low
496h
MA15
MA14
MA13
MA12
–
–
–
MRBE
x0h
MRBH#
MMR Base Address High
497h
MA23
MA22
MA21
MA20
MA19
MA18
MA17
MA16
xx
MICFG#
ClkOut Tri-St Enable
1 = Enabled
499h
–
–
–
–
–
–
–
CLKOE
01h
CS
Code Segment
443h
00h
DS
Data Segment
441h
00h
ES
Extra Segment
442h
00h
33F
33E
33D
33C
33B
33A
339
338
IEH*
Interrupt Enable High
427h
EHSWR3
EHSWR2
EHSWR1
EHSWR0
–
EAuto
ESC23
ESC01
00h
337
336
335
334
333
332
331
330
IEL*
Interrupt Enable Low
426h
EA
EDMAH
EDMAL
EX2
ET1
EX1
ET0
EX0
00h
IPA0
Interrupt Priority A0
4A0h
–
PT0
–
PX0
00h
IPA1
Interrupt Priority A1
4A1h
–
PT1
–
PX1
00h
IPA2
Interrupt Priority A2
4A2h
–
PDMAL
–
PX2
00h
IPA3
Interrupt Priority A3
4A3h
Reserved
–
PDMAH
00h
IPA4
Interrupt Priority A4
4A4h
–
PSC23
–
PSC01
00h
IPA5
Interrupt Priority A5
4A5h
–
–
–
PAutoB
00h
IPA6
Interrupt Priority A6
4A6h
–
PHSWR1
–
PHSWR0
00h
IPA7
Interrupt Priority A7
4A7h
–
PHSWR3
–
PHSWR2
00h
387
386
385
384
383
382
381
380
P0*
Port 0
430h
FFh
38F
38E
38D
38C
38B
38A
389
388
P1*
Port 1
431h
FFh
397
396
395
394
393
392
391
390
P2*
Port 2
432h
FFh
39F
39E
39D
39C
39B
39A
399
398
P3*
Port 3
433h
FFh