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參數(shù)資料
| 型號： | XA-H4 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 16-bit microcontroller |
| 中文描述： | 單片16位微控制器 |
| 文件頁數(shù)： | 19/42頁 |
| 文件大小： | 225K |
| 代理商： | XA-H4 |
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Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
19
Watchdog Timer
This timer is a standard XA-G3 Watchdog Timer. See the G3
datasheet in IC25. Also, if you intend to use the Watchdog Timer to
assert the ResetOut pin, see “ResetOut” in the XA-H4 User Manual
The Watchdog Timer is enabled at reset, and must be periodically
fed to prevent timeout. If the watchdog times out, it will generate an
internal reset; if ResetOut is enabled, the internal reset will generate
a ResetOut pulse (active low pulse on ResetOut pin.)
Reset
On the XA-H4 there are two pins associated with reset. The ResetIn
pin provides an external reset into the XA-H4. The port pin
P3.2_Timer0_ResetOut output can be configured as ResetOut.
Because ResetOut does not reflect ResetIn, the ResetOut pin can
be tied directly back into the ResetIn pin without other PC board
logic. This configuration will make all resets (internal or external)
appear to the XA as external resets. See the XA-H4 User Manualfor
a full discussion of the reset functions.
ResetIn
The ResetIn function is the standard XA-G3 ResetIn function. The
ResetIn signal does NOT get passed on to ResetOut. See the
XA-H4 User Manualfor details on reset.
ResetOut
The P3.2_Timer0_ResetOut pin provides an external indication (if the
ResetOut function is enabled in the RSRSRC register) via an active
low output when an internal reset occurs (internal reset is Reset
instruction or Watchdog time out.) If the ResetOut function is enabled,
the ResetOut pin will be driven low when a Watchdog reset occurs or
the Reset instruction is executed. This signal may be used to inform
other devices in the system that the XA-H4 has been internally reset.
The ResetIn signal does NOT get passed on to ResetOut. When
activated, the duration of the ResetOut pulse is 256 system clocks.
WARNING:
At power on time, from the time that power coming up is
valid, the P3.2_Timer0_ResetOut pin may be driven low for any
period from zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Reset Source Register
The Reset Source Identification Register (RSTSRC) indicates the
cause of the most recent XA reset. The cause may have been an
externally applied reset signal, execution of the RESET instruction, or
a Watchdog reset. Figure 2 shows the fields in the RSTSRC register.
If the ResetOut function is tied back into the ResetIn pin, then all
resets will be external resets, and will thus appear as external resets
in the reset source register. RSTSRC[7] enables the ResetOut
function; 1 = Enabled, 0 = Disabled. See XA-H4 User Manualfor
details; RSTSRC[7] differs in function from most other XA derivatives.
RSTSRC.7
RSTSRC.6
RSTSRC.5
RSTSRC.4
RSTSRC.3
RSTSRC.2
RSTSRC.1
RSTSRC.0
ROEN
–
–
–
–
R_WD
R_CMD
R_EXT
ResetOut function enable bit – see XA-H3 User Manualfor details
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Indicates that the last reset was caused by a watchdog timer overflow (see WARNING.)
Indicates that the last reset was caused by execution of the RESET instruction (see WARNING.)
Indicates that the last reset was caused by the external ResetIn input.
RSTSRC
Not Bit Addressable
Reset Value = see below
ROEN
—
—
—
—
R_WD
R_CMD
R_EXT
BIT
SYMBOL
FUNCTION
WARNING:
If ResetOut function is tied back into ResetIn pin, RSTSRC will always show external reset ONLY, because external reset always takes
precedence over internal reset.
SU01237
Reg Type and Address = SFR 463h
LSB
MSB
Figure 2. RSTSRC reset source register
DRAM CONTROLLER AND MEMORY / I/O BUS
INTERFACE (MIF)
In the memory or system bus interface terminology, generic bus cycles
are synonymous with SRAM bus cycles, because these cycles are
designed to service SRAMs, Flash, EEPROM, peripheral chips, etc.
Chip select output pins function as either CS or RAS (DRAMS and
thus RAS on X-4H only) depending on whether the memory bank has
been programmed as generic or DRAM.
The XA-H4 has a highly programmable memory bus interface with a
complete complete onboard DRAM controller. Most DRAMs (up to
8 MB per RAS pin), SRAMs, Flash, ROMs, and peripheral chips can
be connected to this interface with zero glue chips. The bus interface
provides 6 mappable chip select outputs, five of which can be
programmed to function as RAS strobes to DRAM. CAS generation,
proper address multiplexing for a wide range of DRAM sizes, and
refresh are all generated onboard. The bus timing for each individual
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