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參數(shù)資料
| 型號(hào)： | XA-H4 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 16-bit microcontroller |
| 中文描述： | 單片16位微控制器 |
| 文件頁數(shù)： | 23/42頁 |
| 文件大?。?/td> | 225K |
| 代理商： | XA-H4 |
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Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
23
Receive DMA Channel Modes
The Rx DMA channels have four DMA modes specifically designed
for various applications of the attached USARTs. These modes are
summarized in Table 6. For full details on implementation and use,
see the XA-H4 User Manual
Table 6. Rx DMA modes summary
Mode
Byte Count Source
Maskable Interrupt
Description
SDLC/HDLC
Rx Chaining
DMA stores byte count in header in
memory with data packet.
At end of received packet
When a complete or aborted SDLC/HDLC packet has
been received, the packet byte count and status
information are stored in memory with the packet. A
maskable interrupt is generated.
Periodic
Interrupt
Loaded by processor into DMA,
used only to determine the number
of bytes between interrupts.
Processor can infer the byte count
from the DMA address pointer.
When Byte Counter reaches
zero and is reloaded by
DMA hardware from the byte
count register.
The DMA channel runs until commanded to stop by the
processor. It generates a maskable interrupt once per n
bytes, where nis the number written once into the byte
count register by the processor, thus an interrupt is
generated once every nreceived bytes.
Asynchronous
Character
Time Out
Byte Count can be calculated by
software from the DMA address
pointer.
If no character is received
within a specified time out
period, then interrupt.
Processor specifies time out period between incoming
characters. If no character is received within that time,
a maskable interrupt is generated.
Asynchronous
Character
Match
Byte Count can be calculated by
software from the DMA address
pointer.
When matched character is
stored in memory.
There are four match registers, each incoming character
is received within that time, a maskable interrupt is
generated. When a matched character is stored in
memory by DMA, a maskable interrupt is generated.
SU01240
Data FIFO 3
Data FIFO 1
Data FIFO 2
Data FIFO 0
DMA Control
Segment
Buffer Base
Buffer Bound
Address Pointer
Byte Count
FIFO Control
Rx Time Out
Data FIFO 3
Data FIFO 1
Data FIFO 2
Data FIFO 0
Rx Channel
Tx Channel
DMA Control
Segment
Buffer Base
Buffer Bound
Address Pointer
Byte Count
FIFO Control
Figure 5. Rx and Tx DMA Registers
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