參數(shù)資料
型號(hào): XA-H4
廠商: NXP Semiconductors N.V.
英文描述: Single-chip 16-bit microcontroller
中文描述: 單片16位微控制器
文件頁數(shù): 37/42頁
文件大小: 225K
代理商: XA-H4
Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
37
SU01285
t
CHAV
RAS
ADDR
ClkOut
OE
D[7:0]
CASL
A
RAS
t
AVSL
t
CHSL
Note 2
MS Byte
LS Byte
t
DIS
t
CHAH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CAS ADDR
Even
CAS ADDR
ODD
CAS ADDR
Even
CAS ADDR
ODD
Note 2
t
CHSH
t
CHSH
t
AVSL
MS Byte
LS Byte
t
CHSH
t
DIH
t
CPWH
t
OHDE
t
CHSL
4-Byte Fetch is shown on 8-bit bus, burst can be 2 to 16 bytes.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example).
t
DIH
Figure 18. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8-Bit Bus
SU01286
t
CHSL
t
CHSH
t
AVSL
t
CHAV
RAS ADDRESS
t
OHDE
t
AVSL
Note 4
t
CPWL
t
CHAH
ClkOut
OE
D[7:0]
CASL
A
RAS
LS Byte
MS Byte
LS Byte
MS Byte
Note 4
Note 3
1
2
3
4
5
6
7
8
9
10
11
12
t
CPWH
t
CHSH
t
DIS
t
CHSL
t
CHSH
Note.
4-Byte Fetch is shown on 8-bit bus, burst can be 2 to 16 bytes.
To meet Hold Time, EDO DRAM drives Data until OE rises, or until a new falling edge of CAS.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 8, 10, and 12 in this example).
CAS ADDR
EVEN
CAS ADDR
ODD
CAS ADDR
EVEN
CAS ADDR
ODD
Figure 19. EDO DRAM Burst Code Fetch on 8-Bit Bus
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