參數(shù)資料
型號(hào)： XA-H4
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 16-bit microcontroller
中文描述： 單片16位微控制器
文件頁數(shù)： 15/42頁
文件大?。?/td> 225K
代理商： XA-H4
Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
15
MMR Name
Reset
Value
Description
Address
Offset
Size
Read/Write
or Read Only
USART3 Registers
8
8C0h
8
8C2h
8
8C4h
8
8C6h
8
8C8h
8
8CAh
8
8CCh
8
8CEh
8
8D0h
8
8D2h
8
8D4h
8
8D6h
8
8D8h
8
8DAh
8
8DCh
8
8DEh
8
8E8h
8
8EAh
8
8E0h
8
8E2h
8E4h
8
8E6h
8
8ECh
8
8EEh
8
8F0h
8F2h
8
8F4h
8F6-8FEh
USART3 Write Register 0
USART3 Write Register 1
USART3 Write Register 2
USART3 Write Register 3
USART3 Write Register 4
USART3 Write Register 5
USART3 Write Register 6
USART3 Write Register 7
USART3 Write Register 8
USART3 Write Register 9
USART3 Write Register 10
USART3 Write Register 11
USART3 Write Register 12
USART3 Write Register 13
USART3 Write Register 14
USART3 Write Register 15
USART3 Write Register 16
USART3 Write Register 17
USART3 Read Register 0
USART3 Read Register 1
Reserved
USART3 Read Register 3
USART3 Read Register 6
USART3 Read Register 7
USART3 Read Register 8
Reserved
USART3 Read Register 10
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Command register
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx miscellaneous parameters & mode
Tx parameter and control
HDLC/SDLC address field or Match Character 0
HDLC/SDLC flag or Match Character 1
Transmit Data Buffer
Master Interrupt control
Miscellaneous Tx/Rx control register
Clock Mode Control
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Miscellaneous Control bits
External/Status interrupt control
Match Character 2 (WR16)
Match Character 3 (WR17)
Tx/Rx buffer and external status
Receive condition status/residue code
00h
xx
xx
00h
00h
00h
00h
xx
xx
xx
00h
xx
00h
00h
xx
f8h
00h
00h
RO
RO
RO
RO
Interrupt Pending Bits
SDLC byte count low register
SDLC byte count high and FIFO status
Receive Buffer
–
RO
Loop/clock status
Rx DMA Registers
8
100h
8
101h
8
102h
DMA Control Register Ch.0 Rx
FIFO Control & Status Reg Ch.0 Rx
Segment Register Ch.0 Rx
R/W
R/W
R/W
Control Register
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
10Ch = Byte 0 = older,
10Dh = Byte 1 = younger
10Eh = Byte 2 = older,
10Fh = Byte 3 = younger
Control Register
Control & Status Register
Points to 64 k data segment
00h
00h
00h
Buffer Base Register Ch.0 Rx
R/W
8
104h
00h
Buffer Bound Register Ch.0 Rx
Address Pointer Reg Ch.0 Rx
R/W
R/W
16
16
106h
108h
0000h
0000h
Byte Count Register Ch.0 Rx
R/W
16
10Ah
0000h
Data FIFO Register Ch.0 Lo Rx
R/W
16
10Ch
00h
00h
00h
00h
00h
00h
00h
Data FIFO Register Ch.0 Hi Rx
R/W
16
10Eh
DMA Control Register Ch.1 Rx
FIFO Control & Status Register Ch.1 Rx
Segment Register Ch. 1 Rx
R/W
R/W
R/W
8
8
8
110h
111h
112h
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