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參數(shù)資料
| 型號： | XA-H4 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 16-bit microcontroller |
| 中文描述： | 單片16位微控制器 |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 225K |
| 代理商： | XA-H4 |
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Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
24
DMA Registers
In addition to the 16-bit Global DMA Interrupt Register (which is shared
by all eight DMA channels), each DMA channel has seven control
registers and a four-byte Data FIFO. The four Rx DMA channels have
one additional register, the Rx Character Time Out Register. All DMA
registers can be read and written in Memory Mapped Register (MMR)
space. These registers are summarized below.
Global DMA Interrupt Register (not shown in figure): All DMA
interrupt flags are in this register .
DMA Control Register: Contains the master mode select and
interrupt enable bits for the channel.
Segment Register: Holds A23–A16 (the current segment) of the
24-bit data buffer address.
Buffer Base Register: Holds a pointer (A15–A8) to the lowest byte
in the memory buffer.
Buffer Bound Register: Points to the first out-of-bounds address
above a circular buffer.
Address Pointer Register: Points to a single byte or word in the
data buffer in memory. The 24-bit DMA address is formed by
with the contents of the Address Pointer Register [A15–A0].
Byte Count Register: Holds the initial number of bytes to be
transferred. In Tx Chaining mode, this register is not used
because the byte count is brought into the byte counter from
buffer headers in memory.
FIFO Control & Status Register: Holds the queuing order and
full/empty status for the Data FIFO Registers.
Data FIFO Registers: A four-byte data FIFO buffer internal to the
DMA channel.
Rx Char Time Out Register (RxCTOR, Rx DMA channels only):
Holds the initial value for an 8-bit character timeout countdown
timer which can generate an interrupt.
Four USARTS
Asynchronous features:
–
Asynchronous transfers up to
921.6 kbps
–
Can monitor input stream for up to four match characters per
receiver (H4 only)
–
5, 6, 7, or 8 data bits per character
–
1, 1.5, or 2 Stop bits per character
–
Even or Odd parity generate and check
–
Parity, Rx Overrun, and Framing Error detection
–
Break detection
–
Supports hardware Autobaud detection and response up to
921.6 kbps.
SDLC/HDLC features:
–
Automatic Flag and Abort Character generation and recognition
–
Automatic CRC generation and checking (can be disabled for
“pass-thru”)
–
Automatic zero-bit insertion and stripping
–
Automatic partial byte residue code generation
–
14-bit Packet byte count stored in memory with received packet
by DMA
Synchronous character-oriented protocol features (XA-H4 only):
–
Automatic CRC generation and checking
–
External Sync option
Data encoding/decoding options:
–
FM0 (Biphase Space)
–
FM1 (Biphase Mark)
–
NRZ
–
NRZI
Programmable Baud Rate Generator
Auto Echo and Local Loopback modes
Autobaud Detectors
Each USART has its own Autobaud detector, capable of baud rate
detection up to 921.6 kbaud. The detectors can be programmed to
automatically echo the industry standard autobaud sequences. They
can be programmed to update the necessary control registers in the
USARTs and turn on the receiver, which in turn will automatically
initiate DMA into memory of received data. Thus, once the baud rate
is determined, reception begins without intervention from the
processor. When the baud rate is detected, a maskable interrupt is
sent to the processor. See the “Autobaud” chapter in the XA-H4
User Manualfor details.
I/O Port Output Configuration
Port input/output configurations are the same as standard XA ports:
open drain, quasi-bidirectional, push-pull, and off (off means tri-state
Hi-Z, and allows the pin to be used as an input.
WARNING:
At
power on time, from the time that power coming up is valid, the
P3.2_Timer0_ResetOut pin may be driven low for any period from
zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Power Reduction Modes
The XA-H4 supports Idle and Power Down modes of power
reduction. The idle mode leaves most peripherals running in order to
allow them to activate the processor when an interrupt is generated.
The power down mode stops the oscillator in order to absolutely
minimize power. The processor can be made to exit power down
mode via a reset or one of the external interrupt inputs (INT0 or
INT1). This will occur if the interrupt is enabled and its priority is
higher than that defined by IM3 through IM0. In power down mode,
the power supply voltage may be reduced to the RAM keep-alive
voltage V
RAM
. This retains the RAM, register, and SFR contents at
the point where power down mode was entered.
WARNING:
V
DD
must be raised to within the operating range before power down
mode is exited.
Interrupts
In the XA architecture, all exceptions, including Reset, are handled in
the same general exception structure. The highest priority exception
is, of course, Reset, and is non-maskable. All exceptions are vectored
through the Exception Vector Table in low memory. Coming out of
Reset, these vectors must be stored in non-volatile memory based at
location 000000. Later in the boot sequence, DRAM or SRAM can be
mapped into this address space if desired. There is a feature in the
XA-H4 Memory Controller called “Bank Swap” that supports replacing
the ROM vector table and other low memory with RAM. See the
XA-H4 User Manualfor details.
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