參數(shù)資料
型號： XE8807AMI026TLF
廠商： Semtech
文件頁數(shù)： 108/143頁
文件大?。?/td> 0K
描述： IC MCU LOW PWR MTP FLASH 32-TQFP
標準包裝： 1
系列： XE880x
應用： 感測機
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（11 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
包裝： 標準包裝
供應商設備封裝： 32-TQFP（7x7）
產品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱： XE8807AMI026DKR
Semtech 2006
www.semtech.com
11-4
XE8806A/XE8807A
pos.
RegPACtrl
rw
reset
description
7:1
[7:1]
r
0000000
Unused
0
DebFast
r w
0 nresetpconf
0 = slow debounce, 1 = fastdebounce
Table 11-8: RegPACtrl
pos.
RegPASnaptorail
rw
reset
description
7:0
PASnaptorail[7:0]
rw
0 nresetpconf
set snap-to-rail input on
Table 11-9: RegPASnaptorail
Note: Depending on the status of the EnResetPConf bit in RegSysCtrl, RegPAEdge, RegPADebounce and
RegPACtrl can be reset by any of the possible system resets or only with power-on reset and NRESET pad.
11.4
Interrupts and events map
Interrupt source
Default mapping in
the interrupt manager
Default mapping in the
event manager
pa_irqbus[5]
RegIrqMid[5]
pa_irqbus[4]
RegIrqMid[4]
pa_irqbus[1]
RegIrqMid[1]
RegEvn[4]
pa_irqbus[0]
RegIrqMid[0]
RegEvn[0]
pa_irqbus[7]
RegIrqLow[7]
pa_irqbus[6]
RegIrqLow[6]
pa_irqbus[3]
RegIrqLow[3]
pa_irqbus[2]
RegIrqLow[2]
11.5
Port A (PA) Operation
The Port A input status (debounced or not) can be read from RegPAin.
Debounce mode:
Each bit in Port A can be individually debounced by setting the corresponding bit in RegPADebounce. After reset,
the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if
height consecutive samples are identical. Selection of the clock is done by bit DebFast in Register RegPACtrl.
DebFast
Clock filter
0
1kHz
1
32kHz
Table 11-10: debounce frequency selection
Note: The tolerance on the debounce frequency depends on the selected clock source. When the external clock is
used, the pulse width will be correct if the input of the low prescaler is set to a frequency close to 32kHz (see clock
block documentation).
Pullups/Snap-to-rail:
Different functions are possible depending on the value of the registers RegPAPullup and RegPASnaptorail.
When the corresponding bit in RegPAPullup is set to 0, the inputs are floating (pullup and pulldown resistors are
disconnected). When the corresponding bit in RegPAPullup is 1 and in RegPASnaptorail is 0, a pullup resistor is
connected to the input pin. Finally, when the corresponding bit in RegPAPullup is 1 and in RegPASnaptorail is 1,
the snap-to-rail function is active.
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