參數(shù)資料
型號(hào): XE8807AMI026TLF
廠商: Semtech
文件頁數(shù): 87/143頁
文件大?。?/td> 0K
描述: IC MCU LOW PWR MTP FLASH 32-TQFP
標(biāo)準(zhǔn)包裝: 1
系列: XE880x
應(yīng)用: 感測(cè)機(jī)
核心處理器: Coolrisc816?
程序存儲(chǔ)器類型: 閃存(11 kB)
控制器系列: XE8000
RAM 容量: 512 x 8
接口: UART,USRT
輸入/輸出數(shù): 24
電源電壓: 2.4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
包裝: 標(biāo)準(zhǔn)包裝
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
配用: XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱: XE8807AMI026DKR
Semtech 2006
www.semtech.com
7-9
XE8806A/XE8807A
The next table summarizes the different clock configurations of the circuit:
Clock Sources
Clock targets
Cpuck
Mode
name
En
Ex
tC
lo
c
k
EnableRc
En
a
b
le
Xt
a
l
CpuSel=0
CpuSel=1
High
Prescaler
Clock
input
Low
Prescaler
Clock
input
Sleep
0
off
Xtal
0
1
Xtal
off
Xtal
RC
0
1
0
RC
NOTE 2
High presc.
RC
High presc.
RC + Xtal
0
1
RC
NOTE 1 and 2
Xtal
RC
NOTE 1
Xtal
External
1
X
External
NOTE
2
High presc.
External
High presc.
Table 7-13: Table of clocking modes.
Note 1: The frequency of the RC must be higher than 100 kHz when Xtal is enabled in order to ensure a proper 32
kHz operation.
Note 2: The clock RC can be divided by the value of freq instruction (see coolrisc instruction information)
freq instruction
cpuck
nodiv
RC or external
div2
RC/2 or external/2
div4
RC/4 or external/4
div8
RC/8 or external/8
div16
RC/16 or external/16
Note 3: Switching from one clock source to another and stopping the unused clock source must be performed
using 2 MOVE instructions to RegSysClock. First select the new clock source and then stop the unused one.
7.10
Prescalers
The clock generator block embeds two divider chains: the high prescaler and the low one.
The high prescaler is made of an 8 stage dividing chain and the low prescaler of a 15 stage dividing chain.
Features:
High prescaler can only be driven with RC clock or external clock (bits EnableRc or EnExtClock have to be
set, see Table 7-13).
Low prescaler can be driven from the high prescaler or directly with the Xtal clock when bit EnableXtal is set
to 1 and bit EnExtClock is set to 0.
Bit ClearLowPrescal in the RegSysPre0 register allows to reset synchronously the low prescaler, the low
prescaler is also automatically cleared when bit EnableXtal is set. Both dividing chains are reset
asynchronously by the nresetglobal signal.
Bit ColdXtal=1 indicates the Xtal is in its start phase. It is active for 32768 Xtal cycles after setting EnableXtal.
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