參數(shù)資料
型號: XE8807AMI026TLF
廠商: Semtech
文件頁數(shù): 62/143頁
文件大小: 0K
描述: IC MCU LOW PWR MTP FLASH 32-TQFP
標(biāo)準(zhǔn)包裝: 1
系列: XE880x
應(yīng)用: 感測機
核心處理器: Coolrisc816?
程序存儲器類型: 閃存(11 kB)
控制器系列: XE8000
RAM 容量: 512 x 8
接口: UART,USRT
輸入/輸出數(shù): 24
電源電壓: 2.4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
包裝: 標(biāo)準(zhǔn)包裝
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
配用: XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱: XE8807AMI026DKR
Semtech 2006
www.semtech.com
4-3
XE8806A/XE8807A
code
access mode
r
bit can be read
w
bit can be written
r0
bit always reads 0
r1
bit always reads 1
c
bit is cleared by writing any value
c1
bit is cleared by writing a 1
ca
bit is cleared after reading
s
special function, verify the detailed description in the respective peripherals
Table 4-1. Access mode codes used in the register definitions
code
reset source
glob
nresetglobal
cold
nresetcold
pconf
nresetpconf
sleep
nresetsleep
Table 4-2. Reset source coding used in the register definitions
4.2.1
Low power data registers (h0000-h0007)
Name
Address
7
6
5
4
3
2
1
0
Reg00
h0000
Reg00[7:0]
rw,00000000,glob
Reg01
h0001
Reg01[7:0]
rw,00000000,glob
Reg02
h0002
Reg02[7:0]
rw,00000000,glob
Reg03
h0003
Reg03[7:0]
rw,00000000,glob
Reg04
h0004
Reg04[7:0]
rw,00000000,glob
Reg05
h0005
Reg05[7:0]
rw,00000000,glob
Reg06
h0006
Reg06[7:0]
rw,00000000,glob
Reg07
h0007
Reg07[7:0]
rw,0000000,glob
Table 4-3. Low power data registers
4.2.2
System, clock configuration and reset configuration (h0010-h001F)
Name
Address
7
6
5
4
3
2
1
0
RegSysCtrl
h0010
SleepEn
rw,0,cold
EnResetPConf
rw,0,cold
EnBusError
rw,0,cold
EnResetWD
rw,0,cold
r0
RegSysReset
h0011
Sleep
rw,0,glob
SleepFlag
rc,0,cold
ResetBusError
rc, 0, cold
ResetWD
rc, 0, cold
ResetfromportA
rc, 0, cold
r0
RegSysClock
h0012
CpuSel
rw,0,sleep
r0
EnExtClock
rw,0,cold
BiasRC
rw,1,cold
ColdXtal
r,1,sleep
r0
EnableXtal
rw,0,sleep
EnableRC
rw,1,sleep
RegSysMisc
h0013
r0
Output16k
rw,0,sleep
OutputCpuCk
rw,0,sleep
RegSysWd
h0014
r0
WatchDog[3:0]
s,0000,glob
RegSysPre0
h0015
r0
ClearLowPresca
l
c1r0,0,-
RegSysRcTrim1
h001B
r0
RcFreqRange
rw,0,cold
RcFreqCoarse[3:0]
rw,0001,cold
RegSysRcTrim2
h001C
r0
RcFreqFine[5:0]
rw,00000,cold
Table 4-4. Reset block and clock block registers
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