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參數(shù)資料
| 型號： | XR16C872 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）) |
| 中文描述： | 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器） |
| 文件頁數(shù)： | 35/60頁 |
| 文件大?。?/td> | 314K |
| 代理商： | XR16C872 |
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XR16C872
35
Rev. P1.00
Preliminary
Modem Status Register (MSR)
This register provides the current state of the control
interface signals from the modem, or other peripheral
device that the UART A or B is connected. Four bits of
this register are used to indicate the changed informa-
tion. These bits are set to a logic 1 whenever a control
input from the modem changes state. These bits are
set to a logic 0 whenever the CPU reads this register.
MSR BIT-0:
Logic 0 = No CTS# Change (normal default condition)
Logic 1 = The CTS# input to the UART has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-1:
Logic 0 = No DSR# Change (normal default condition)
Logic 1 = The DSR# input to the UART has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-2:
Logic 0 = No RI# Change (normal default condition)
Logic 1 = The RI# input to the UART has changed from
a logic 0 to a logic 1. A modem Status Interrupt will be
generated.
MSR BIT-3:
Logic 0 = No CD# Change (normal default condition)
Logic 1 = Indicates that the CD# input to the UART has
changed state since the last time it was read. A modem
Status Interrupt will be generated.
MSR BIT-4:
CTS# functions as hardware flow control signal input if
it is enabled via EFR bit-7. The transmit holding
register flow control is enabled/disabled by MSR bit-4.
Flow control (when enabled) allows suspending and
resuming data transmissions based on the external
modem CTS# signal. A logic 1 at the CTS# pin will
suspend transmissions as soon as current character
has finished transmission.
Normally MSR bit-4 bit is the complement of the CTS#
input. However in the loop-back mode, this bit is
equivalent to the RTS bit in the MCR register.
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the
complement of the DSR# input pin. In the loop-back
mode, this bit is the complement to the DTR bit in the
MCR register.
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the
complement of the RI# input. In the loop-back mode
this bit is equivalent to the OP1# bit in the MCR register.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
complement of the CD# input. In the loop-back mode
this bit is equivalent to the OP2# bit in the MCR register.
Scratch Pad Register (SPR)
The UART A or B has a temporary data register to store
8 bits of user information. The register content is set
to 0xFF upon power up or a hardware reset. This
register is alternately used as TX or RX FIFO counter
register, when FCTR bit-6=1 with EMSR bit-0 defining
for TXCNT or RXCNT.
Enhanced Feature Register (EFR)
This register is only accessible when LCR is set to
0xBF. Enhanced feature functions in the 16C550 base
register set area are enabled using this register bit-4.
These are IER bits 4-7, ISR & FCR bits 4-5, and MCR
bits 5-7.
Bits-0 through 3 provide single or dual character
software flow control selection. When the Xon1 and
Xon2 and/or Xoff1 and Xoff2 modes are selected (see
Table 5), the double 8-bit words are concatenated into
two sequential characters.
EFR BIT 0-3: (logic 0 or cleared is the default condition)
Combinations of software flow control can be selected
by programming these bits.
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