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參數(shù)資料
| 型號： | XR16C872 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）) |
| 中文描述： | 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器） |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 314K |
| 代理商： | XR16C872 |
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XR16C872
38
Rev. P1.00
Preliminary
TRIGGER LEVEL/FIFO COUNT REGISTER (TRG)
This register is only accessible when LCR is set to
0xBF.
This register provides the user programmable transmit
or receive trigger level from byte 0 to 128 (0xFF), and
reading the number of data bytes in the transmit or
receive FIFO.
TRG BIT 0-7: Write only.
This register sets the user programmable transmit or
receive FIFO trigger levels. FCTR bit-7 must be set
and point to the transmitter or receiver prior to
programming the trigger level.
TRG BIT 0-7: Read only.
Transmit / receive FIFO count. Number of characters
in transmit or receive FIFO can be read via this
register. FCTR bit-7 must be set and point to the
transmitter or receiver prior to reading the FIFO count.
ENHANCED MODE SELECT REGISTER (EMSR)
This register is only accessible when LCR is set to
0xBF and FCTR Bit-6 is set to logic 1.
EMSR BIT-0: Write only
0 = Receive FIFO count register. The Scratch Pad
Register (SPR) is used to provide the receive FIFO
count when it is read.
1 = Transmit FIFO count register. The Scratch Pad
Register (SPR) is used to provide the transmit FIFO
count when it is read.
Example to read the number of character count in TX
or RX FIFO.
In the Initialization routine:
set LCR to 0xBF
; point to enhanced registers
set FCTR bit-6 to logic 1
; swap SPR to be FIFO counters and
; point to EMSR register
set LCR to operating parameters
- in RX routine -
set EMSR bit-0 to logic 0
; set to read RX FIFO count
read SPR
; obtain RX FIFO count
or
- in TX routine -
set EMSR bit-0 to logic 1
; read TX FIFO count
read SPR
; obtain TX FIFO Count
EMSR BIT-1: Write only
0 = Normal.
1 = Alternate receive - transmit FIFO count. When
EMSR Bit-0=1 and EMSR Bit-1=1, Scratch Pad Reg-
ister is used to provide the receive - transmit FIFO
count when it is read every alternate read cycle. The
TRG Bit-7 will provide FIFO count mode information,
TRG Bit-7=0 receive mode, TRG Bit-7=1 transmit
mode.
EMSR BIT-2: Write only
This bit is not available in the 872.
EMSR BIT4 and 5 - Write only
These bits select the RTS flow control hysteresis and
are associated with FCTR bit 0 and 1. The RTS
hysteresis is reference to the RX FIFO trigger level.
Below table shows the 16 selectable hysteresis.
EMSR
Bit-5
EMSR
Bit-4
FCTR
Bit-1
FCTR
Bit-0
RTS Hysteresis
(characters)
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Next level
+/- 4
+/- 6
+/- 8
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
+/- 8
+/- 16
+/- 24
+/- 32
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
+/- 12
+/- 20
+/- 28
+/- 36
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
+/- 40
+/- 44
+/- 48
+/- 52
EMSR BIT 6-7:
Reserved for future use.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16L2450 | 2.25V TO 5.5V DUART |
| XR16L2450IJ | 97-3108A20-29S-KIT |
| XR16L2450IM | 2.25V TO 5.5V DUART |
| XR16L2550IJ | LOW VOLTAGE DUART WITH 16-BYTE FIFO |
| XR16L2550IL | LOW VOLTAGE DUART WITH 16-BYTE FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C872CQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16C872IQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16L2450 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
| XR16L2450_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
| XR16L2450IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
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