參數(shù)資料
型號: XR16C872
廠商: Exar Corporation
英文描述: Dual UART with 1284 Parallel Port and Plug-and-Play(PnP) Controller(雙通用異步接收器/發(fā)送器(帶1284雙向并行端口和即插即用控制器))
中文描述: 雙UART)與1284并行端口,插頭插即用(PnP)功能控制器(雙通用異步接收器/發(fā)送器(帶1284雙向并行端口和即插即用控制器)
文件頁數(shù): 45/60頁
文件大?。?/td> 314K
代理商: XR16C872
XR16C872
45
Rev. P1.00
Preliminary
RLE
The module does not support Run Length Encoding
(RLE) compression (indicated by the “0” in CONF-B bit
7) but does support RLE de-compression on the receiv-
ing side.
The host may send compressed data to the peripheral
by writing the RLE length byte (bit 7 = 0) to address 000
(NOTE: DMA cannot be used for this byte) which will
place a zero into the FIFO tag bit. This must be
followed immediately by the data byte being written to
A10 A2A1 A0
Register
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
Data
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
ECP-AFIFO
0
0
0
1
DSR
Busy
ACKE
PE
Select
ERR#
1
1
1
0
0
1
0
DCR
0
0
DIR
INT
enable
SelectIN#
INIT#
AutoFD#
Strobe#
0
0
1
1
EPP-APort
AP-7
AP-6
AP-5
AP-4
AP-3
AP-2
AP-1
AP-0
0
1
0
0
EPP-DPort
PDA-7
PDA-6
PDA-5
PDA-4
PDA-3
PDA-2
PDA-1
PDA-0
0
1
0
1
EPP-DPort
PDB-7
PDB-6
PDB-5
PDB-4
PDB-3
PDB-2
PDB-1
PDB-0
0
1
1
0
EPP-DPort
PDC-7
PDC-6
PDC-5
PDC-4
PDC-3
PDC-2
PDC-1
PDC-0
0
1
1
1
EPP-DPort
PDD-7
PDD-6
PDD-5
PDD-4
PDD-3
PDD-2
PDD-1
PDD-0
1
X
0
0
CONF-A
ECP
INT type
0
0
1
0
FIFO-F
0
0
1
X
0
1
CONF-B
RLE
IRQ
input
IRQ
Sel-2
IRQ
Sel-1
IRQ
Sel-0
DMA
Sel-2
DMA
Sel-1
DMA
Sel-0
1
X
1
0
ECR
Mode
Sel-2
Mode
Sel-1
Mode
Sel-0
Fault
enable
DMA
En/Dis
Service
INT
FIFO
full
FIFO
empty
Table 7. 1284 Control Register Description
the FIFO at address 400. These bytes will be trans-
ferred to the peripheral in the normal manner.
De-compression takes place if PDIR = 1 when data is
read from the FIFO at address 000, 400 or DMA. When
a byte is read from the FIFO, bits 0-6 (length) are
placed in a counter if data bit-7 and the FIFO tag bit are
both low. The subsequent byte in the FIFO (data) is
presented to the host count + 1 times before the FIFO
read pointer is advanced.
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