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參數(shù)資料
| 型號： | XR16C872 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）) |
| 中文描述： | 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器） |
| 文件頁數(shù)： | 42/60頁 |
| 文件大小： | 314K |
| 代理商： | XR16C872 |
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XR16C872
42
Rev. P1.00
Preliminary
OW#
IOR#
DMA
X00
X01
X10
X11
000
001
010
011
3
3
3
3 (default)
Cnfg-B Bit 3-5:
In the PnP mode IRQ assignment is made through auto
configuration. Manual mode defaults to IRQ 7.
IOW#
IOR#
IRQ
000
001
010
011
100
101
110
111
001
001
010
001
001
001
001
111
7
7 (default)
7
7
7
7
7
7
Cnfg-B Bit-6:
Returns the true value of the selected IRQ pad.
Cnfg-B Bit-7:
Indicates RLE compression is not supported.
EXTENDED CONTROL REGISTER ( ECR )
The Extended Control Register has a system RESET
state of 10010101. The significance of the bits is
defined by the ECP specification as:
ECR Bit-0:
This read-only bit returns FIFO empty status (FIFO-E)
and is forced high unless PPF, ECP, or TST mode is
selected.
CONFIGURATION REGISTER B ( Cnfg-B )
This register is available in ECR mode 111 only, and
returns bits 0-5 as logic zero.
Cnfg-B Bit 0-2:
In the PnP mode the DMA channel is assigned through
auto configuration. It defaults to DMA 3 in the manual
mode.
0 = At least one byte of data contains in the FIFO.
1 = FIFO is empty.
ECR Bit-1:
This read-only bit returns FIFO full status (FIFO-F) and
is forced low unless PPF, ECP, or TST mode is
selected.
0 = At least one empty location is available in the FIFO.
1 = FIFO is full.
ECR Bit-2:
When low, this bit (ServiceIntr) enables a pulsed
interrupt and enables DMA requests (if bit-3 is set). If
the enabled interrupt occurs, this bit is automatically
returned to a high. The interrupt conditions are:
ECR Bit-3 = DMA
DCR Bit-5 = DIRection
DMA
DIR
CONDITION
0
0
1
0
1
X
8 empty bytes in the FIFO
8 filled bytes in the FIFO
DMA Terminal Count (TC)
ECR BIT-3:
This bit disables DMA when set low. When set high,
a low on ServiceIntr will enable DMA requests.
0 = DMA disabled, DRQx pin is three-stated.
1 = DMA enabled
ECR Bit-4:
When low, this bit (ErrIntrEn#) enables a pulsed inter-
rupt if ERR# (Fault#) is low. The interrupt is only
enabled in ECP mode.
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