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參數(shù)資料
| 型號： | XR16C872 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）) |
| 中文描述： | 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器） |
| 文件頁數(shù)： | 40/60頁 |
| 文件大小： | 314K |
| 代理商： | XR16C872 |
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XR16C872
40
Rev. P1.00
Preliminary
STANDARD DEFINITIONS
Forward direction only.
Compatible Mode, “Centronics” or standard
mode (SPP).
Reverse direction only.
Nibble mode:
4 bits at a time using status lines for data “Hewlett
Packard Bi-tronics”.
Bi-directional.
EPP:
Enhanced Parallel Port, used primarily by non-
printer peripherals.
ECP:
Extended Capability Port, used primarily by
latest generation of printers, scanners and
external storage and CD drives for higher data
transfer rate.
DATA REGISTER (DATA )
DATA Bit 0-7:
For host output cycles in SPP mode (ECR mode 000)
or PS/2 mode (ECR mode 001), data from the host is
registered at the trailing edge of IOW#. On host input
cycles, data at the peripheral port is passed through to
the host data bus.
ECP FIFO ADDRESS ( ECP-AFIFO )
ECP-AFIFO Bit 0-7:
This port is only available for programmed I/O (non-
DMA), and only has significance for host write. Data
written to this port is stored in the FIFO if FIFO-F = 0
and will be lost if FIFO-F = 1. A 9th FIFO bit (tag) is
set low on write. A read from this port is the same as
a read at 400.
DATA STATUS REGISTER ( DSR )
This status register is read-only except for bit-0, and all
bits are latched for the duration of IOR#.
DSR Bit-0:
If EPP mode is not selected, this bit returns logic one.
During EPP mode, bit-0 will return a high if the EPP 10
msecond TimeOut elapsed during the last EPP read or
write cycle (this TimeOut also aborts the EPP cycle).
This status bit is cleared by exiting EPP mode or by the
host writing a high to bit-0 of this register.
DSR Bit 1-2:
Reserved, logic one.
DSR Bit-3:
The true state of the ERR# pin.
DSR Bit-4:
The true state of the SELECT pin.
DSR Bit-5:
The true state of the PE pin.
DSR Bit-6:
The true state of the ACK# pin.
DSR Bit-7:
The complement of the BUSY pad.
DATA CONTROL REGISTER ( DCR )
DCR Bit-0:
The complement of this bit drives STROBE#, and the
complement of the pad state is returned for read.
DCR Bit-1:
The complement of this bit drives AUTOFD#, and the
complement of the pad state is returned for read.
DCR Bit-2:
This bit drives INIT#, and the pad state is returned for
read.
DCR Bit-3:
The complement of this bit drives SELCTIN#, and the
complement of the pad state is returned for read.
相關PDF資料 |
PDF描述 |
|---|---|
| XR16L2450 | 2.25V TO 5.5V DUART |
| XR16L2450IJ | 97-3108A20-29S-KIT |
| XR16L2450IM | 2.25V TO 5.5V DUART |
| XR16L2550IJ | LOW VOLTAGE DUART WITH 16-BYTE FIFO |
| XR16L2550IL | LOW VOLTAGE DUART WITH 16-BYTE FIFO |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C872CQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16C872IQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16L2450 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
| XR16L2450_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
| XR16L2450IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
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