參數(shù)資料
型號(hào)： XR16C872
廠商： Exar Corporation
英文描述： Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）)
中文描述： 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）
文件頁(yè)數(shù)： 39/60頁(yè)
文件大?。?/td> 314K
代理商： XR16C872
XR16C872
39
Rev. P1.00
Preliminary
On a reset, the device defaults to compatible mode
which is the standard PC Centronics printer mode in PC
computers. The EPP, and ECP modes can only be
activated by programming the Extended Control Reg-
ister (ECR), this requires address bit A10=1, which is
outside the normal parallel port address in the ISA I/O
space. The internal timing is designed to operate from
a 22.1184 MHz clock which is supplied from an
external source on pin XTAL1 or by the built-in oscilla-
tor circuit with an appropriate crystal.
Optional capabilities of the ECP specification are set
as follows:
ECP defined interrupts are pulsed, low true
(Centronics ACK# is non-pulsed, low true).
PWord size is forced to 1 byte.
There is 1 byte in the transmitter that does
not affect the FIFO full bit (ECP modes).
RLE compression is not supported in hardware.
IRQ channel is selectable as 5, 7, or 9.
DMA channel is selectable as 3.
FIFO THRESHOLD is set at 8 (used only for
non-DMA access to the FIFO).
Port
Address
Read/Write
Mode
Function
DATA
ECP-AFIFO
DSR
DCR
EPP-APort
EPP-DPort
C-FIFO
ECP-DFIFO
T-FIFO
Cnfg-A
Cnfg-B
ECR
000
000
001
002
003
R/W
W
R
R/W
R/W
R/W
W
R/W
R/W
R
R-R/W
R/W
000
011
All
All
100
100
010
011
110
111
111
All
Data port
ECP FIFO (Address)
Status Register
Control Register
EPP Port (Address)
EPP Port (Data)
Parallel Port Data FIFO
ECP FIFO (Data)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
004-007
400
400
400
400
401
402
Table 6. Parallel Data Port Internal Register
1284 Controller
The bi-directional parallel data port controller is com-
patible to IEEE Standard 1284 interface. The 1284
interface can be programmed as a standard printer port
or bi-directional parallel port for high speed data trans-
fer systems. The 1284 interface provides 1284 Level II
electrical interface, needing no external transceivers
to interface to the parallel port cable. Hence, it can
connect directly to a printer or a high speed bi-direc-
tional parallel device. The 1284 controller supports the
following modes of operation.
Standard Centronics interface, forward only.
Bi-directional Centronics.
Parallel port with data FIFO.
ECP, Extended Capabilities Port, and with 16
byte data FIFO in Forward and Reverse
modes, supports Run Length Encoded (RLE)
de-compression in the reverse mode, however,
no compression is supported in the forward
mode, and Direct Memory Access transfer
capability.
EPP, Enhanced Parallel Port.
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