
35
x r
PRELIMINARY
E3 UNI FOR ATM
XRT7234
REV. P1.0.0
156
TxGFCClk
O
Transmit GFC Nibble Field Serial Input Port Clock:
This signal, along
with TxGFC, and TxGFCMSB combine to function as the “Transmit GFC
Nibble-field” serial input port. The “Transmit GFC Nibble-field” serial input
port uses this output clock signal to sample the values applied to the
TxGFC pin, on its rising edge. This pin will provide four rising edges for
each valid cell being transmitted.
100
157
ALE_AS
I
Address Latch Enable/Address Strobe:
This input is used to latch the
address (present at the Microprocessor Interface Address Bus, A[8:0]) into
the UNI Microprocessor Interface circuitry and to indicate the start of a
READ/WRITE cycle. This input is active-high in the Intel Mode (MOTO =
“l(fā)ow”) and active-low in the Motorola Mode (MOTO = “high”).
158
TxGFC
I
Transmit GFC Nibble-Field Serial Input Port:
This signal, along with
TxGFCClk and TxGFCMSB combine to function as the “Transmit GFC
Nibble-field” serial input port. The user will specify the value of the GFC
field, within a given valid (user or OAM) ATM cell, by serial transmitting
its four bit value into this input. Each of these four bits will clocked into
the UNI via rising edge of the TxGFCClk clock output signal.
Note:
The “Transmit GFC Nibble-field” Serial input port will only insert
the GFC Nibble field value into valid cells. Therefore, this input pin will
only read in the GFC Nibble value when a valid cell is being processed.
1
159
GND
***
Ground Signal Pin
2
160
Rdy_Dtck
O
READY or DTACK:
This “active-low” output pin will function as the READY
output, when the microprocessor interface is running in the “Intel” Mode; and
will function as the DTACK output, when the microprocessor interface is
running in the “Motorola” Mode.
“Intel” Mode—READY Output:
When the UNI negates this output pin
(e.g., toggles it “l(fā)ow”), it indicates (to the
μ
P
) that the current READ or
WRITE cycle is to be extended until this signal is asserted (e.g., toggled
“high”).
“Motorola” Mode—DTACK (Data Transfer Acknowledge) Output:
The UNI device will assert this pin in order to inform the local micropro-
cessor that the present READ or WRITE cycle is nearly complete. If the UNI
device requires that the current READ or WRITE cycle be extended, then
the UNI will delay its assertion of this signal. The 68000 family of
μ
P
s
requires this signal from its peripheral devices, in order to quickly and
properly complete a READ or WRITE cycle.
PIN DESCRIPTION (CONTINUED)
Pin
No.
100 Pin Package
Pin No. 160
PinPackage
Symbol
Type
Description