
13
x r
PRELIMINARY
E3 UNI FOR ATM
XRT7234
REV. P1.0.0
t36
Delay Time from rising edge of RxOHClk to
valid data at RxOH
ns
t37
Bit Period of data at RxOH
ns
Symbol
Parameter
Min.
Typ
Max.
Units
Conditions
Receive E3 Framer (LIU Interface Port) —See Figures 97 and 98
t38
RxPOS/RxNEG data Setup Time to rising
edge of RxLineClk
ns
Receive E3 Framer is con-
figured to sample RxPOS
and RxNEG on the rising
edge of RxLineClk.
t39
RxPOS/RxNEG data Hold Time from rising edge
of RxLineClk
ns
Receive E3 Framer is con-
figured to sample RxPOS
and RxNEG on the rising
edge of RxLineClk.
t40
RxPOS/RxNEG data Setup Time to falling edge
of RxLineClk
ns
Receive E3 Framer is con-
figured to sample RxPOS
and RxNEG on the falling
edge of RxLineClk.
t41
RxPOS/RxNEG data Hold Time from falling edge
of RxLineClk
ns
Receive E3 Framer is con-
figured to sample RxPOS
and RxNEG on the falling
edge of RxLineClk.
fRxLineClk
Clock frequency of RxLineClk
Hz
t42
Period of RxLineClk clock signal
ns
Receive Cell Processor (GFC Serial Output Port) —See Figure 99
t47
Clock Period of RxGFCClk
ns
t48
Delay from rising edge of RxGFCClk to rising edge
of RxGFCMSB pin.
ns
t49
Pulsewidth of RxGFCMSB signal
ns
t50
Delay from rising edge of RxGFCMSB signal to
first valid bit at RxGFC.
ns
t51
Delay from rising edge of RxGFCClk to valid bit
at RxGFC.
ns
t52
Pulsewidth of Bit at RxGFC output.
ns
Receive Utopia Interface Block (See Figure 100)
t53
Delay time from rising edge of RxClk to Data Valid
at RxData[15:0]
ns
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Test Conditions: TA = 25°C, VCC = 5.0V ± 5% unless otherwise specified
Symbol
Parameter
Min.
Typ
Max.
Units
Conditions