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XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.0
7
The Test Cell Generator can generate test cells in
“One Shot” Mode (e.g., a burst of 1024 test cells) or in
“Continuous” Mode (e.g., a continuous stream of
test cells).
The Test Cell Receiver will identify and collect the
Test Cells for further analyses, based upon the
“user-defined” header byte patterns. Additionally,
the Test Cell Receiver will report the occurrence of
any errors by incrementing an on-chip register.
FOR CLEAR-CHANNEL FRAMING APPLICATIONS
Contains an internal PRBS pattern generator and
receiver. The PRBS pattern generator will generate
and insert a PRBS pattern into the DS3 payload
bits.
The PRBS receiver will receive these DS3 frames,
and will attempt to acquire “PRBS Lock” with this
DS3 frame data. Additionally, the PRBS Receiver
will report the occurrence of any errors by incre-
menting an on-chip register.
LINE INTERFACE DRIVE AND SCAN SECTION
The Line Interface Drive and Scan Section allows the
user to monitor and control many aspects of the
XRT73L04 E3/DS3/STS-1 Line Interface Unit, via on-
chip registers, within the UNI IC. This feature elimi-
nates the need for glue logic to interface the
XRT72L74 DS3 UNI/Framer to the XRT73L04 DS3
Line Interface Unit IC.
The On-Chip Line Interface Drive register allows
the user to control the state of 6 output pins. The
function of these output pins, when asserted, are
tabulated below.
CLEAR CHANNEL MODE OPERATION
Signal Name
Function of Output Pin
Req
Receive Equalizer By-Pass:
“1” configures the XRT73L04 to shut off its internal Receive Equalizer.
“0” configures the XRT73L04 to enable its internal Receive Equalizer.
TAOS
Transmit “All Ones” Pattern.
“1” configures the XRT73L04 LIU IC to overwrite the DS3 data that is output via the TxPOS and
TxNEG outputs, and transmit an “All Ones” pattern onto the line.
“0” configures the XRT73L04 LIU IC to transmit data, as is applied to it via the TPDATA and TNDATA
input pins.
EncoDis
B3ZS Encoder Disable/Enable Select.
"1" disables the B3ZS Encoder, within the XRT73L04.
"0" enables the B3ZS Decoder within the XRT73L04.
TxLev
Transmit Output Signal Line Build Out Select.
Setting this bit-field to “1” disables the Transmit Line Build Out circuitry within the XRT73L04. In this
case, the XRT73L04 will generate an “unshaped” square wave signal out onto the line (via the TTIP
and TRING output pins).
Note: In order to configure the XRT73L04 to generate a line signal that complies with the Transmit Output
Pulse Template Requirements (per Bellcore GR-499-CORE), this setting is advised if the cable length
between the Transmit Output of the XRT73L04 and the DSX-3 Cross-Connect is greater than 225 feet.
Setting this bit-field to “0” enables the Transmit Line Build Out circuitry within the XRT73L04. In this
case, the XRT73L04 will generate a “shaped” square wave out onto the line (via the TTIP and TRING
output pins).
Note: In order to configure the XRT73L04 to generate a line signal that complies with the Transmit Output
Pulse Template Requirements (per Bellcore GR-499-CORE), this setting is advised if the cable length
between the Transmit Output of the XRT73L04 and the DSX-3 Cross-Connect is less than 225 feet.