參數(shù)資料
型號： XRT72L74
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 67/104頁
文件大?。?/td> 1301K
代理商： XRT72L74
á
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.0
67
T
ABLE
32:
T
X
DS3 LAPD S
TATUS
/I
NTERRUPT
R
EGISTER
R
EGISTER
31 T
X
DS3 LAPD S
TATUS
/I
NTERRUPT
R
EGISTER
H
EX
A
DDRESS
: 0
X
1F
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-4
Unused
RO
0
3
Tx DL Start
R/W
0
0 to 1 transition configures the LAPD Transmitter to begin its transmission of
the PMDL (or LAPD Message) consisting of the data residing within the
“Transmit LAPD Message” buffer.
N
OTE
:
This bit-field is only active if the XRT72L74 has been configured to
support the “C-bit Parity” Framing format.
2
Tx DL Busy
RO
0
0: LAPD Transmitter is NOT currently transmitting a LAPD Message to the
Remote Terminal Equipment; and is not available to transmit a new LAPD
Message.
1: LAPD Transmitter is currently transmitting a LAPD Message to the
Remote Terminal Equipment.
N
OTE
:
This bit-field is only active if the XRT72L74 has been config-
ured to support the “C-bit Parity” Framing format.
1
Tx LAPD Interrupt Enable
R/W
0
0: “Completion of Transmission of LAPD Message” Interrupt is disabled.
1: “Completion of Transmission of LAPD Message” Interrupt is enabled. The
XRT72L74 will generate an interrupt, anytime the LAPD Transmitter has
completed its transmission of a given LAPD Message.
N
OTE
:
This bit-field is only active if the XRT72L74 has been configured to
support the “C-bit Parity” Framing format.
0
Tx LAPD Interrupt Status
RUR
0
0: “Completion of Transmission of LAPD Message” interrupt has NOT
occurred since the last read of this register.
1: “Completion of Transmission of LAPD Message” interrupt has occurred
since the last read of this register.
N
OTE
:
This bit-field is only active if the XRT72L74 has been configured to
support the “C-bit Parity” Framing format.
T
ABLE
33:
PMON LCV E
VENT
C
OUNT
R
EGISTER
- MSB
R
EGISTER
32 PMON LCV E
VENT
C
OUNT
R
EGISTER
- MSB H
EX
A
DDRESS
: 0
X
20
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
LCV Count High byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON LCV Event Count Reg-
ister - LSB” contains the 16-bit value for the total number of Line Code Viola-
tions that have been detected since the last read of this register.
This register contains the “High” Byte of this 16-bit expression.
N
OTE
:
This register is only active if the “B3ZS Decoder” (within the
XRT72L74) has been enabled.
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