參數(shù)資料
型號： XRT72L74
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 27/104頁
文件大?。?/td> 1301K
代理商： XRT72L74
á
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.0
27
P1
R3
R2
R1
TxPOHIns_0
TxPOHIns_1
TxPOHIns_2
TxPOHIns_3
I
Transmit PLCP Frame POH Data Insert Enable:
This input can be asserted to allow the user to input his/her own value for the
PLCP POH bytes via the TxPOH input pin, in each PLCP frame, prior to transmis-
sion. If this input pin is not asserted, then the UNI will generate its own PLCP POH
bytes.
N
OTE
:
The user should tie this input pin to “GND” if the XRT72L74 is going to be
configured to operate in either the “Clear-Channel-Framer” Mode or in the “Direct-
Mapped ATM” Mode.
Rx PLCP Processor
U25
U26
T24
T25
RxOHInd/
RxPFrame_0
RxOHInd/
RxPFrame_1
RxOHInd/
RxPFrame_2
RxOHInd/
RxPFrame_3
O
Receive Overhead Bit Indicator/PLCP Frame Boundary Indicator
Output—Receive PLCP Processor.
The exact functionality of this output pin depends upon whether the XRT72L71
UNI/Framer IC is operating in the Clear Channel or ATM Uni Mode.
Clear Channel Mode - RxOHInd:
In clear channel mode, this pin is pulsed “High” for one bit period whenever an over-
head bit is being output via the RxSerData output pin. In other words, the “RxSer-
Data” output pin will contain an over-head if this pin is sampled “High”.
ATM UNI Mode:
This output pin pulses “High” when the Receive PLCP Processor is receiving the last
bit of a given PLCP frame.
L24
L25
L26
L23
RxPLOF_0
RxPLOF_1
RxPLOF_2
RxPLOF_3
O
Receive PLCP—“Loss of Frame” Output Indicator:
The Receive PLCP Processor will assert this pin, when it declares a “Loss of
Frame” condition. This output will be negated when the Receive PLCP Processor
reaches the “In Frame” Condition.
N
OTE
:
This output pin is only active if the user has configured the XRT72L74 to
operate in the “ATM UNI” Mode.
T26
T23
R24
R25
RxPOHFrame_0
RxPOHFrame_1
RxPOHFrame_2
RxPOHFrame_3
O
Receive PLCP Frame Path Overhead (POH) Byte Serial Output Port—Begin-
ning of Frame Signal Pin:
This output pin, along with RxPOH, RxPOHClk, and RxPOHIns pins comprise the
“Receive PLCP Frame POH Byte” serial output port. This output pin provides fram-
ing information to external circuitry receiving and processing this POH (Path Over-
head) data, by pulsing “High” when the first bit of the Z6 byte is output via the
RxPOH output pin. This pin is “Low” at all other times during this PLCP POH fram-
ing cycle.
N
OTE
:
This output pin is only active if the XRT72L74 has been configued to oper-
ate in the “ATM UNI” Mode.
Receive PLCP “Out of Frame” Indicator:
The Receive PLCP Processor will assert this pin, when it declares an “Out of
Frame” condition. This output will be negated when the Receive PLCP Processor
reaches the “In Frame” Condition.
N
OTE
:
This output pin is only active if the user has configured the XRT72L74 to
operate in the “ATM UNI” Mode.
Receiver Red Alarm Indicator—Receive PLCP Processor:
The UNI asserts this output pin to denote that one of the following events has been
detected by the Receive PLCP Processor:
OOF—Out of Frame Condition
LOF—Loss of Frame Condition
N
OTE
:
This output pin is only active whenever the XRT72L74 has been configured
to operate in the “ATM UNI” Mode.
V25
V26
V23
U24
RxPOOF_0
RxPOOF_1
RxPOOF_2
RxPOOF_3
O
K24
K25
K26
J24
RxPRed_0
RxPRed_1
RxPRed_2
RxPRed_3
O
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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