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參數(shù)資料
| 型號： | XRT72L74 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 29/104頁 |
| 文件大?。?/td> | 1301K |
| 代理商： | XRT72L74 |
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XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.0
29
AB24
AB26
AA25
AA26
RxGFCMSB_0
RxGFCMSB_1
RxGFCMSB_2
RxGFCMSB_3
O
Received GFC Nibble Field—MSB Indicator
:
This output pin functions as a part of the “Receive GFC-Nibble Field” Serial Output
port; which also consists of the RxGFC and RxGFCClk pins. This pin pulses
“High” the instant that the MSB (Most Significant Bit) of a GFC Nibble is being out-
put on the RxGFC pin.
N
OTE
:
This output pin is only active if the XRT72L74 has been configured to oper-
ate in the “ATM UNI” Mode.
W24
W25
W26
V24
RxLCD_0
RxLCD_1
RxLCD_2
RxLCD_3
O
Loss of Cell Delineation Indicator:
This active-"High" output pin will be asserted whenever the Receive Cell Proces-
sor has experienced a “Loss of Cell Delineation”. This pin will return “Low” once
the Receive Cell Processor has regained Cell Delineation.
N
OTE
:
This output pin is only active if the XRT72L74 has been configured to oper-
ate in the “ATM UNI” Mode.
Tx UTOPIA Interface
AC11
AF11
AE11
AD11
AF10
TxUAddr0
TxUAddr1
TxUAddr2
TxUAddr3
TxUAddr4
I
Transmit UTOPIA Address Bus Input:
These pins comprise the Transmit UTOPIA Address Bus input pins. The Transmit
UTOPIA Address Bus is only in use when the UNI is operating in the M-PHY
mode. When the ATM Layer processor wishes to write data to a particular UNI
device, it will provide the address of the “intended UNI” on the Transmit UTOPIA
Address Bus. The contents of the Transmit UTOPIA Address Bus input pins are
sampled on the rising edge of TxUClk. The DS3 UNI will compare the data on the
Transmit UTOPIA Address Bus with the pre-programmed contents of the TxUT
Address Register (Address = 70h). If these two values are identical and the
TxUEN pin is asserted, then the TxUClav pin will be driven to the appropriate state
(based upon the TxFIFO fill level) for the Cell Level handshake mode of operation.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L74 has
been configured to operate in either the “Clear-Channel-Framer” Mode or in the
“Single-PHY” Mode.
Transmit UTOPIA Interface—Cell Available Output Pin:
This output pin supports data flow control between the ATM Layer processor and
the Transmit UTOPIA Interface block. The exact functionality of this pin depends
upon whether the UNI is operating in the “Octet Level” or “Cell Level” handshaking
mode.
Octet Level Handshaking:
When the Transmit UTOPIA Interface block is operat-
ing in the octet-level handshaking mode, this signal is negated (toggles “Low”)
when the TxFIFO is not capable of handling four more write operations; by the
ATM Layer processor to the Transmit UTOPIA Interface block. This signal will be
asserted when the TxFIFO is capable of receiving four or more write operations of
ATM cell data.
Cell Level Handshaking:
When the Transmit UTOPIA Interface block is operating
the cell-level handshaking mode, this signal is asserted (toggles “High”) when the
TxFIFO is capable of receiving at least one more full cell of data from the ATM
Layer processor. This signal is negated, if the TxFIFO is not capable of receiving
one more full cell of data from the ATM Layer processor.
Multi-PHY Operation:
When the UNI chip is operating in the Multi-PHY mode, this
signal will be tri-stated until the TxUClk cycle following the assertion of a valid
address on the Transmit UTOPIA Address bus input pins (e.g., when the contents
on the Transmit UTOPIA Address bus pins match that within the Transmit UTOPIA
Address Register). Afterwards, this output pin will behave in accordance with the
cell-level handshake mode.
N
OTE
:
This output pin is only active if the XRT72L74 has been configured to oper-
ate in the “ATM UNI” Mode.
AD8
TxUClav
O
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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