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參數(shù)資料
| 型號： | XRT73L02 |
| 廠商： | Exar Corporation |
| 英文描述： | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 14/62頁 |
| 文件大?。?/td> | 716K |
| 代理商： | XRT73L02 |
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XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.1.0
á
PRELIMINARY
10
50
RPOS_1
O
Receive Positive Data Output - Channel 1:
This output pin pulses “High" whenever Channel 1 of the XRT73L02 has
received a Positive Polarity pulse in the incoming line signal at the RTIP_1/
RRing_1 inputs.
N
OTE
:
If the Channel 1 B3ZS/HDB3 Decoder is enabled, then the zero sup-
pression patterns in the incoming line signal (such as: "00V", "000V", "B0V",
"B00V") is not reflected at this output.
51
RNEG_1
O
Receive Negative Data Output - Channel 1:
This output pin pulses "High" whenever Channel 1 of the XRT73L02 has
received a Negative Polarity pulse in the incoming line signal at the RTIP_1/
RRing_1 inputs.
N
OTE
:
If the Channel 1 B3ZS/HDB3 Decoder is enabled, then the zero sup-
pression patterns in the incoming line signal (such as: "00V", "000V", "B0V",
"B00V") is not reflected at this output.
52
RxClk_1
O
Receive Clock Output pin - Channel 1:
This output pin is the Recovered Clock signal from the incoming line signal for
Channel 1. The receive section of Channel 1 outputs data via the RPOS_1
and RNEG_1 output pins on the rising edge of this clock signal.
N
OTE
:
The Receive Section of Channel 1 is configured to update the data on
the RPOS_1 and RNEG_1 output pins on the falling edge of RxClk_1 by doing
one of the following:
a.
Operating in the Hardware Mode
Pull the RxClkINV pin to "High".
b.
Operating in the HOST Mode
Write a "1" into the RxClkINV bit-field of the Command Register.
53
LOSMUTEN
I
MUTE-upon-LOS Enable Input (Hardware Mode):
This input pin is used to configure the XRT73L02 while it is operating in the
Hardware Mode to MUTE the recovered data via the RPOS_(n), RNEG_(n)
output pins whenever one of the Channels declares an LOS condition.
Setting this input pin "High" configures all Channels to automatically pull the
RPOS_(n) and RNEG_(n) output pins to GND whenever it is declaring an LOS
condition, MUTing the data being output to the Terminal Equipment.
Setting this input pin "Low" configures all Channels to NOT automatically
MUTE the recovered data whenever an LOS condition is declared.
N
OTES
:
1. This input pin is ignored and should be connected to GND if the
XRT73L02 is operating in the HOST Mode.
2. This pin is internally pulled "High".
54
DVDD_1
****
Receive Digital VDD - Channel 1
55
AGND_1
****
Analog Ground (Substrate Connection) - Channel 1
56
DGND_1
****
Transmit Digital GND - Channel 1
57
DMO_1
O
Drive Monitor Output - Channel 1:
If no transmitted AMI signal is present on MTIP_1 and MRing_1 input pins for
128±32 TxClk periods, then DMO_1 toggles and remains "High" until the next
AMI signal is detected.
PIN DESCRIPTION
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03BIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L02M | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L02MIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L02MIVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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