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參數(shù)資料
| 型號： | XRT73L02 |
| 廠商： | Exar Corporation |
| 英文描述： | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 55/62頁 |
| 文件大?。?/td> | 716K |
| 代理商： | XRT73L02 |
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XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
51
set to "1" if the Clock Recovery PLL is out of lock with
the incoming line signal.
Bit D3 - RLOS_(n) (Receive Loss of Signal Status -
Channel (n))
This Read-Only bit-field indicates whether or not
Channel (n) of the Receiver is currently declaring an
LOS (Loss of Signal) Condition.
This bit-field is set to "0" if Channel (n) is NOT cur-
rently declaring the LOS Condition or, this bit-field is
set to "1" if Channel (n) is declaring an LOS Condi-
tion.
Bit D2 - ALOS_(n) (Analog Loss of Signal Status -
Channel (n))
This Read-Only bit-field indicates whether or not the
Channel (n) Analog LOS Detector is currently declar-
ing an LOS condition.
This bit-field is set to "0" if the Analog LOS Detector is
NOT currently declaring an LOS condition. This bit-
field is set to "1" if the Analog LOS Detector is cur-
rently declaring an LOS condition.
N
OTE
:
The purpose is to isolate the Detector (e.g., either
the Analog LOS or the Digital LOS detector) that is declar-
ing the LOS condition. This feature may be useful for trou-
bleshooting/debugging purposes.
Bit D1 - DLOS_(n) (Digital Loss of Signal Status -
Channel (n))
This Read-Only bit-field indicates whether or not the
Channel (n) Digital LOS Detector is currently declar-
ing an LOS condition.
This bit-field is set to "0" if the Digital LOS Detector is
NOT currently declaring an LOS condition. This bit-
field is set to "1" if the Digital LOS Detector is current-
ly declaring an LOS condition.
N
OTE
:
The purpose is to isolate the Detector (e.g., either
the Analog LOS or the Digital LOS detector) that is declar-
ing the LOS condition. This feature may be useful for trou-
bleshooting/debugging purposes.
Bit D0 - DMO_(n) (Drive Monitor Output Status -
Channel (n))
This Read-Only bit-field reflects the status of the
DMO output pin.
5.2.2
Command Register CR1
The bit-format and default values for Command Reg-
ister CR1-(n) are listed below followed by the function
of these bit-fields.
COMMAND REGISTER CR1-(N)
Bit D4 - TxOFF_(n) (Transmitter OFF - Channel (n))
This Read/Write bit-field is used to turn off the Chan-
nel (n) Transmitter.
Writing a "1" to this bit field turns off the Transmitter
and tri-state the Transmit Output. Writing a "0" to this
bit-field turns on the Transmitter.
Bit D3 - TAOS_(n) (Transmit All OneS - Channel
(n))
This Read/Write bit-field is used to command the
Channel (n) Transmitter to generate and transmit an
all “1’s” pattern onto the line.
Writing a "1" to this bit-field commands the Transmit-
ter to transmit an all “1’s” pattern onto the line. Writ-
ing a "0" to this bit-field commands normal operation.
Bit D2 - TxClkINV_(n) (Transmit Clock Invert -
Channel (n))
This Read/Write bit-field is used to configure the
Transmitter in the XRT73L02 to sample the signal at
the TPData and TNData pins on the rising edge or
falling edge of TxClk (the Transmit Line Clock signal).
Writing a "1" to this bit-field configures the Transmitter
to sample the TPData and TNData input pins on the
rising edge of TxClk. Writing a "0" to this bit-field con-
figures the Transmitter to sample the TPData and
TNData input pins on the falling edge of TxClk.
Bit D1 - TxLEV_(n) (Transmit Line Build-Out En-
able/Disable Select - Channel (n))
This Read/Write bit-field is used to enable or disable
the Channel (n) Transmit Line Build-Out circuit in the
XRT73L02.
Setting this bit-field "High” disables the Channel (n)
Line Build-Out circuit. In this mode, Channel (n) out-
puts partially-shaped pulses onto the line via the
TTIP_(n) and TRing_(n) output pins.
Setting this bit-field "Low" enables the Channel (n)
Line Build-Out circuit. In this mode, Channel (n) out-
puts shaped pulses onto the line via the TTIP_(n) and
TRing_(n) output pins.
In order to comply with the Isolated DSX-3/STSX-1
Pulse Template Requirements (per Bellcore GR-499-
CORE or GR-253-CORE):
a. Set this bit-field to "1" if the cable length between
the Cross-Connect and the transmit output of Chan-
nel (n) is greater than 225 feet.
D4
D3
D2
D1
D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n)
0
0
0
0
0
COMMAND REGISTER CR1-(N)
D4
D3
D2
D1
D0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03BIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L02M | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L02MIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L02MIVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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