參數(shù)資料
型號: XRT73L02
廠商: Exar Corporation
英文描述: 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述: 2頻道E3/DS3/STS-1線路接口單元(2通道E3/DS3/STS-1線接口單元)
文件頁數(shù): 29/62頁
文件大?。?/td> 716K
代理商: XRT73L02
á
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
25
b. Operating in the HOST Mode.
To configure the Data Rate of a Channel, write the
appropriate values into the STS-1/DS3_Ch_(n) and
E3_Ch_(n) bit-fields in Command Register CR4-(n).
N
OTE
:
Reference Table 2 for the correct address of each
channel.
COMMAND REGISTER CR4-(N)
Table 4 relates the values of these two bit-fields to the
selected data rates.
T
ABLE
4: S
ELECTING
THE
D
ATA
R
ATE
FOR
C
HANNEL
(
N
)
OF
THE
XRT73L02
VIA
THE
STS-1/DS3_C
H
_(
N
)
AND
THE
E3_C
H
_(
N
)
BIT
-
FIELDS
IN
THE
A
PPROPRIATE
C
OMMAND
R
EGISTER
(HOST M
ODE
)
Making these selections does the following:
Configure the VCO Center Frequency of Channel
(n) of the Clock Recovery Phase-Locked Loop to
match the selected data rate.
If the DS3 or STS-1 data rates are selected, it con-
figures the B3ZS/(HDB3) Encoder and Decoder
blocks to support B3ZS Encoding/Decoding.
If the E3 data rate is selected, it configures the
B3ZS/(HDB3) Encoder and Decoder blocks to sup-
port HDB3 Encoding/Decoding.
Configure the on-chip Pulse-Shaping circuitry to
generate Transmit Output pulses of the appropriate
shape and width to meet the applicable pulse tem-
plate requirement.
Establishes the LOS Declaration/Clearance Criteria
for Channel (n) (Section 3.5).
2.0
THE TRANSMIT SECTION
Figure 6 shows the Transmit Section in each Channel
of the XRT73L02 consists of the following blocks:
Transmit Logic Block
TxClk_(n) Duty Cycle Adjust Block
HDB3/(B3ZS) Encoder
Pulse Shaping Block
The purpose of the Transmit Section in each Channel
of the XRT73L02 is to take TTL/CMOS level data
from the Terminal Equipment and encode it into a for-
mat that can:
1.
be efficiently transmitted over coaxial cable at E3,
DS3 or STS-1 data rates,
2.
be reliably received by the Remote Terminal
Equipment at the other end of the E3, DS3 or
STS-1 data link, and
3.
comply with the applicable pulse template
requirements.
The circuitry that the Transmit Section in each Chan-
nel of the XRT73L02 takes to accomplish this goal is
discussed below.
2.1
T
HE
T
RANSMIT
L
OGIC
B
LOCK
The purpose of the Transmit Logic Block is to accept
either Dual-Rail or Single-Rail (binary data stream)
TTL/CMOS level data and timing information from the
Terminal Equipment.
2.1.1
Accepting Dual-Rail Data from the Termi-
nal Equipment
Whenever the XRT73L02 accepts Dual-Rail data
from the Terminal Equipment, it does so via the fol-
lowing input signals:
TPData_(n)
TNData_(n)
TxClk_(n)
Figure 7 illustrates the typical interface for the trans-
mission of data in a Dual-Rail Format between the
Terminal Equipment and the Transmit Section of the
XRT73L02.
STS-1 (51.84 Mbps)
0
1
B3ZS
T
ABLE
3: S
ELECTING
THE
D
ATA
R
ATE
FOR
C
HANNEL
(
N
)
OF
THE
XRT73L02,
VIA
THE
E3_C
H
_(
N
)
AND
STS-1/
DS3_C
H
_(
N
)
INPUT
PINS
(H
ARDWARE
M
ODE
)
D
ATA
R
ATE
S
TATE
OF
E3_C
H
_(
N
) P
IN
(P
IN
20
OR
39)
S
TATE
OF
STS-1/DS3_CH_(
N
)
P
IN
(P
IN
21
OR
41)
M
ODE
OF
B3ZS/HDB3 E
NCODER
/
D
ECODER
B
LOCKS
D4
D3
D2
D1
D0
X
STS-1/(DS3)_(n) E3_Ch_(n) LLB_(n) RLB_(n)
X
X
X
X
Xs
S
ELECTED
D
ATA
R
ATE
STS-1/
DS3_C
H
_(
N
) (D3)
E3_C
H
_(
N
)
(D2)
E3
X (Don't Care)
1
DS3
0
0
STS-1
1
0
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