- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376461 > XRT73L02 (Exar Corporation) 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) PDF資料下載
參數(shù)資料
| 型號： | XRT73L02 |
| 廠商： | Exar Corporation |
| 英文描述： | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 39/62頁 |
| 文件大?。?/td> | 716K |
| 代理商： | XRT73L02 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
á
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
35
ceive a line signal with an overall cable length of 300
feet or greater. Conversely, turn OFF the Receive
Equalizer if the Receive Section of a given channel is
going to receive a line signal with an overall cable
length of less than 300 feet.
N
OTES
:
1. If the Receive Equalizer block is turned ON when it
is receiving a line signal over short cable length the
received line signal may be over-equalized, which
could degrade performance by increasing the
amount of jitter that exists in the recovered data
and clock signals or by creating bit-errors.
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the trans-
mitting terminal to the receiving terminal. However,
the Receive Equalizer was not designed to counter
flat loss where all of the Fourier frequency compo-
nents within the line signal are subject to the same
amount of attenuation. Flat loss is handled by the
AGC block.
Disable the Receive Equalizer block by doing either of
the following:
a. Operating in the Hardware Mode
Set the REQEN_(n) input pin "Low".
b. Operating in the HOST Mode
Write a "0" to the REQEN_(n) bit-field in Command
Register CR2.
3.3
P
EAK
D
ETECTOR
AND
S
LICER
After the incoming line signal has passed through the
Receive Equalizer block, it is routed to the Slicer
block. The Slicer block quantifies a given bit-period
(or symbol) within the incoming line signal as either a
“1” or a “0”.
3.4
C
LOCK
R
ECOVERY
PLL
The purpose of the Clock Recovery PLL is to track
the incoming Dual-Rail data stream and to derive and
generate a recovered clock signal.
It is important to note that the Clock Recovery PLL re-
quires a line rate clock signal at the ExClk input pin.
The Clock Recovery PLL operates in one of two
modes:
The Training Mode
The Data/Clock Recovery Mode
3.4.1
The Training Mode
If a given channel in the XRT73L02 is not receiving a
line signal via the RTIP and RRing input pins, or if the
frequency difference between the line signal and that
applied via the ExClk input pin exceeds 0.5%, the
channel operates in the Training Mode. When the
channel is operating in the Training Mode, it does the
following:
a.
Declare a Loss of Lock indication by toggling its
respective RLOL_(n) output pin “High".
b.
Output a clock signal via the RxClk_(n) output pin
which is derived from the signal applied to the
EXClk_(n) input pin.
3.4.2
The Data/Clock Recovery Mode
If the frequency difference between the line signal
and that applied via the ExClk input pin is less than
0.5%, the channel operates in the Data/Clock Recov-
ery mode. In this mode, the Clock Recovery PLL
locks onto the line signal via the RTIP and RRing in-
put pins.
3.5
T
HE
HDB3/B3ZS D
ECODER
The Remote Transmitting Terminal typically encodes
the line signal into some sort of Zero Suppression
Line Code (e.g., HDB3 for E3 and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process of this data from
the Near-End Receiving Terminal. However, once the
data has made it across the E3, DS3 or STS-1 Trans-
port Medium and has been recovered by the Clock
Recovery PLL, it is now necessary to restore the orig-
inal content of the data. The purpose of the HDB3/
B3ZS Decoding block is to restore the data transmit-
ted over the E3, DS3 or STS-1 line to its original con-
tent prior to Zero Suppression Coding.
3.5.1
B3ZS Decoding DS3/STS-1 Applications
If the XRT73L02 is configured to operate in the DS3
or STS-1 Modes, then the HDB3/B3ZS Decoding
Blocks perform B3ZS Decoding. When the Decoders
are operating in this mode, each of the Decoders
parses through its respective incoming Dual-Rail data
COMMAND REGISTER CR2_(N)
D4
D3
D2
D1
D0
RESERVED
ENDECDIS_(n)
ALOSDIS_(n)
DLOSDIS_(n)
REQEN_(n)
X
X
X
X
0
相關PDF資料 |
PDF描述 |
|---|---|
| XRT73L03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03BIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L02M | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MES | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L02MIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L02MIVTR-F | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。