參數(shù)資料
型號(hào): XRT73L02
廠商: Exar Corporation
英文描述: 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述: 2頻道E3/DS3/STS-1線路接口單元(2通道E3/DS3/STS-1線接口單元)
文件頁(yè)數(shù): 46/62頁(yè)
文件大?。?/td> 716K
代理商: XRT73L02
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.1.0
á
PRELIMINARY
42
RxClk_(n) is the Recovered Clock signal from the in-
coming Received line signal. As a result, these clock
signals are typically 34.368 MHz for E3 applications,
44.736 MHz for DS3 applications and 51.84 MHz for
SONET STS-1 applications.
In general, if a given channel received a positive-po-
larity pulse in the incoming line signal via the
RTIP_(n) and RRing_(n) input pins, then the channel
pulses its corresponding RPOS_(n) output pin "High".
If the channel received a negative-polarity pulse in
the incoming line signal via the RTIP_(n) and
RRing_(n) input pins, then the Channel (n) pulses its
corresponding RNEG_(n) output pin "High".
Inverting the RxClk_(n) outputs
Both channels can invert the RxClk_(n) signals with
respect to the delivery of the RPOS_(n) and
RNEG_(n) output data to the Receiving Terminal
Equipment. This feature may be useful for those cus-
tomers whose Receiving Terminal Equipment is de-
signed such that the RPOS_(n) and RNEG_(n) data
must be sampled on the rising edge of RxClk_(n).
Figure 24 illustrates the behavior of the RPOS_(n),
RNEG_(n) and RxClk_(n) signals when the
RxClk_(n) signal has been inverted.
a. Operating in the Hardware Mode
Setting the RxClkINV pin “High” results in all chan-
nels of the XRT73L02 to output the recovered data on
RPOS_(n) and RNEG_(n) on the falling edge of
RxClk_(n). Setting this pin “Low” results in the recov-
ered data on RPOS_(n) and RNEG_(n) to output on
the rising edge of RxClk_(n).
b. Operating in the HOST Mode
In order to configure a channel of the XRT73L02 to
invert the RxClk_(n) output signal, the XRT73L02
must be operating in the HOST Mode.
To invert RxClk_(n) associated with Channel (n), write
a "1" into the RxClk_(n)INV bit-field in Command
Register CR-3 as illustrated below.
F
IGURE
23. H
OW
THE
XRT73L02
OUTPUTS
DATA
ON
THE
RPOS
AND
RNEG
OUTPUT
PINS
RxClk
RPOS
RNEG
F
IGURE
24. T
HE
B
EHAVIOR
OF
THE
RPOS, RNEG
AND
R
X
C
LK
SIGNALS
WHEN
R
X
C
LK
IS
INVERTED
RxClk
RPOS
RNEG
相關(guān)PDF資料
PDF描述
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03BIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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