參數(shù)資料
型號： XRT73L02
廠商： Exar Corporation
英文描述： 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述： 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元）
文件頁數(shù)： 41/62頁
文件大小： 716K
代理商： XRT73L02
á
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
37
b. Operating in the Hardware Mode
To globally enable all HDB3/B3ZS Decoder blocks in
the XRT73L02, pull the ENDEC_DIS input pin “Low".
To globally disable all HDB3/B3ZS Decoder blocks in
the XRT73L02 and configure the XRT73L02 to trans-
mit and receive in an AMI format, pull the
ENDEC_DIS input pin "High".
3.6
LOS D
ECLARATION
/C
LEARANCE
Each channel of the XRT73L02 contains circuitry that
monitors the following two parameters associated
with the incoming line signals.
1.
The amplitude of the incoming line signal via the
RTIP and RRing inputs.
2.
The number of pulses detected in the incoming
line signal within a certain amount of time.
If a given channel of the XRT73L02 determines that
the incoming line signal is missing due to either insuf-
ficient amplitude or a lack of pulses in the incoming
line signal, it declares a Loss of Signal (LOS) condi-
tion. The channel declares the LOS condition by tog-
gling its respective RLOS_(n) output pin “High” and
by setting its corresponding RLOS_(n) bit field in
Command Register 0 or Command Register 8 to "1".
Conversely, if the channel determines that the incom-
ing line signal has been restored (e.g., there is suffi-
cient amplitude and pulses in the incoming line sig-
nal), it clears the LOS condition by toggling its re-
spective RLOS_(n) output pin "Low" and setting its
corresponding RLOS_(n) bit-field to "0".
In general, the LOS Declaration/Clearance scheme
that is employed in the XRT73L02 is based upon ITU-
T Recommendation G.775 for both E3 and DS3 appli-
cations.
3.6.1
The LOS Declaration/Clearance Criteria
for E3 Applications
When the XRT73L02 is operating in the E3 Mode, a
given channel declares an LOS Condition if its re-
ceive line signal amplitude drops to -35dB or below.
Further, the channel clears the LOS Condition if its
receive line signal amplitude rises back to -15dB or
above. Figure 20 illustrates the signal levels at which
each channel of the XRT73L02 declares and clears
LOS.
COMMAND REGISTER CR2-(N)
D4
D3
D2
D1
D0
Reserved
ENDEC_DIS
ALOSDIS_(n)
DLOSDIS_(n)
REQEN_(n)
X
0
X
X
1
相關(guān)PDF資料
PDF描述
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03BIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT73L02M 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02MES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT73L02MIV 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02MIV-F 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT73L02MIVTR-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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