參數(shù)資料
型號: XRT73L02
廠商: Exar Corporation
英文描述: 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述: 2頻道E3/DS3/STS-1線路接口單元(2通道E3/DS3/STS-1線接口單元)
文件頁數(shù): 8/62頁
文件大?。?/td> 716K
代理商: XRT73L02
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.1.0
á
PRELIMINARY
4
8
Host/(HW)
I
HOST/Hardware Mode Select:
This input pin is used to enable or disable the Microprocessor Serial Interface
(e.g., consisting of the SDI, SDO, SClk, and CS pins).
Setting this input pin "High" enables the Microprocessor Serial Interface (e.g.
configures the XRT73L02 to operate in the HOST Mode). In this mode, con-
figure the XRT73L02 via the Microprocessor Serial Interface. When the
XRT73L02 is operating in the HOST Mode, then it ignores the states of many
of the discrete input pins.
Setting this input pin "Low" disables the Microprocessor Serial Interface (e.g.,
configures the XRT73L02 to operate in the Hardware Mode). In this mode,
many of the external input control pins are functional.
9
RxClk_0
O
Receive Clock Output pin - Channel 0:
This output pin is the Recovered Clock signal from the incoming line signal for
Channel 0. The receive section of Channel 0 outputs data via the RPOS_0
and RNEG_0 output pins on the rising edge of this clock signal.
N
OTE
:
The Receive Section of Channel 0 is configured to update the data on
the RPOS_0 and RNEG_0 output pins on the falling edge of RxClk_0 by doing
one of the following:
a. Operating in the Hardware Mode
Pull the RClkINV pin to "High".
b. Operating in the HOST Mode
Write a "1" into the RClkINV bit-field within the Command Register.
10
RNEG_0
O
Receive Negative Data Output - Channel 0:
This output pin pulses "High" whenever Channel 0 of the XRT73L02 has
received a Negative Polarity pulse in the incoming line signal at the RTIP_0/
RRing_0 inputs.
N
OTE
:
If the Channel 0 B3ZS/HDB3 Decoder is enabled, then the zero sup-
pression patterns in the incoming line signal (such as: "00V", "000V", "B0V",
"B00V") is not reflected at this output.
11
RPOS_0
O
Receive Positive Pulse Output - Channel 0:
This output pin pulses "High" whenever Channel 0 of the XRT73L02 has
received a Positive Polarity pulse in the incoming line signal at the RTIP_0/
RRing_0 inputs.
N
OTE
:
If the Channel 0 B3ZS/HDB3 Decoder is enabled, then the zero sup-
pression patterns in the incoming line signal (such as: "00V", "000V", "B0V",
"B00V") is not reflected at this output.
12
DGND_0
****
Receive Digital GND - Channel 0
13
RLOS_0
O
Receive Loss of Signal Output Indicator - Channel 0:
This output pin toggles "High" if Channel 0 in the XRT73L02 has detected a
Loss of Signal Condition in the incoming line signal.
The criteria the XRT73L02 uses to declare an LOS Condition depends upon
whether it is operating in the E3 or STS-1/DS3 Mode.
PIN DESCRIPTION
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03BIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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