XRT73L04
4 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
á
PRELIMINARY
REV. P1.0.5
III
LIST OF FIGURES
F
IGURE
1. XRT73L04 B
LOCK
D
IAGRAM
............................................................................................................ 1
F
IGURE
2. M
ULTI
C
HANNEL
ATM A
PPLICATION
................................................................................................... 2
F
IGURE
3. M
ULTI
S
ERVICE
- F
RAME
R
ELAY
A
PPLICATION
.................................................................................... 2
F
IGURE
4. P
IN
OUT
OF
THE
XRT73L04
IN
THE
144 P
IN
TQFP
PACKAGE
............................................................ 3
F
IGURE
5. T
RANSMIT
P
ULSE
A
MPLITUDE
T
EST
C
IRCUIT
FOR
E3, DS3
AND
STS-1 R
ATES
(
TYPICAL
CHANNEL
) .. 16
F
IGURE
6. T
IMING
D
IAGRAM
OF
THE
T
RANSMIT
T
ERMINAL
I
NPUT
I
NTERFACE
..................................................... 16
F
IGURE
7. T
IMING
D
IAGRAM
OF
THE
R
ECEIVE
T
ERMINAL
O
UTPUT
I
NTERFACE
.................................................... 16
F
IGURE
8. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
D
ATA
S
TRUCTURE
................................................................ 21
F
IGURE
9. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
.................................................... 21
F
IGURE
10. F
UNCTIONAL
B
LOCK
D
IAGRAM
OF
THE
XRT73L04 ........................................................................ 23
F
IGURE
11. T
HE
TYPICAL
INTERFACE
FOR
THE
T
RANSMISSION
OF
D
ATA
IN
A
D
UAL
-R
AIL
F
ORMAT
FROM
THE
T
RANS
-
MITTING
T
ERMINAL
E
QUIPMENT
TO
THE
T
RANSMIT
S
ECTION
OF
A
CHANNEL
.................................... 26
F
IGURE
12. T
HE
XRT73L04 S
AMPLES
THE
DATA
ON
THE
TPD
ATA
AND
TND
ATA
INPUT
PINS
............................ 27
F
IGURE
13. T
HE
B
EHAVIOR
OF
THE
TPD
ATA
AND
T
X
C
LK
I
NPUT
S
GNALS
,
WHILE
THE
T
RANSMIT
L
OGIC
B
LOCK
IS
A
C
-
CEPTING
S
INGLE
-R
AIL
D
ATA
FROM
THE
T
ERMINAL
E
QUIPMENT
....................................................... 27
F
IGURE
14. A
N
E
XAMPLE
OF
B3ZS E
NCODING
................................................................................................. 28
F
IGURE
15. A
N
E
XAMPLE
OF
HDB3 E
NCODING
................................................................................................ 29
F
IGURE
16. T
HE
B
ELLCORE
GR-499-CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE
FOR
DS3 A
PPLICATIONS
.... 30
F
IGURE
17. T
HE
B
ELLCORE
GR-253-CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE
FOR
SONET STS-1 A
PPLICA
-
TIONS
............................................................................................................................................ 31
F
IGURE
18. R
ECOMMENDED
S
CHEMATIC
FOR
I
NTERFACING
THE
T
RANSMIT
S
ECTION
OF
THE
XRT73L04
TO
THE
L
INE
.......................................................................................................................................................32
F
IGURE
19. R
ECOMMENDED
S
CHEMATIC
FOR
I
NTERFACING
THE
R
ECEIVE
S
ECTION
OF
THE
XRT73L04
TO
THE
L
INE
(T
RANSFORMER
-C
OUPLING
) ........................................................................................................... 34
F
IGURE
20. R
ECOMMENDED
S
CHEMATIC
FOR
I
NTERFACING
THE
R
ECEIVE
S
ECTION
OF
THE
XRT73L04
TO
THE
L
INE
(C
APACITIVE
-C
OUPLING
) ............................................................................................................... 34
F
IGURE
21. T
HE
T
YPICAL
A
PPLICATION
FOR
THE
S
YSTEM
I
NSTALLER
............................................................... 35
F
IGURE
22. A
N
E
XAMPLE
OF
B3ZS D
ECODING
................................................................................................ 37
F
IGURE
23. A
N
E
XAMPLE
OF
HDB3 D
ECODING
................................................................................................ 37
F
IGURE
24. T
HE
S
IGNAL
L
EVELS
THAT
THE
XRT73L04
DECLARES
AND
CLEARS
LOS ...................................... 38
F
IGURE
25. T
HE
B
EHAVIOR
THE
LOS O
UTPUT
I
NDICATOR
IN
RESPONSE
TO
THE
L
OSS
OF
S
IGNAL
AND
THE
R
ESTO
-
RATION
OF
S
IGNAL
........................................................................................................................ 39
F
IGURE
26. T
HE
TYPICAL
INTERFACE
FOR
THE
T
RANSMISSION
OF
D
ATA
IN
A
D
UAL
-R
AIL
F
ORMAT
,
FROM
THE
R
ECEIVE
S
ECTION
OF
THE
XRT73L04
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
......................................... 42
F
IGURE
27. H
OW
THE
XRT73L04
OUTPUTS
DATA
ON
THE
RPOS
AND
RNEG
OUTPUT
PINS
.............................. 42
F
IGURE
28. T
HE
B
EHAVIOR
OF
THE
RPOS, RNEG,
AND
R
X
C
LK
SIGNALS
WHEN
R
X
C
LK
IS
INVERTED
................ 43
F
IGURE
29. T
HE
TYPICAL
INTERFACE
FOR
THE
T
RANSMISSION
OF
D
ATA
IN
A
S
INGLE
-R
AIL
F
ORMAT
FROM
THE
R
E
-
CEIVE
S
ECTION
OF
THE
XRT73L04
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
................................ 44
F
IGURE
30. T
HE
BEHAVIOR
OF
THE
RPOS
AND
R
X
C
LK
OUTPUT
SIGNALS
WHILE
THE
XRT73L04
IS
TRANSMITTING
S
INGLE
-R
AIL
DATA
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
........................................................ 44
F
IGURE
31. A
CHANNEL
OPERATING
IN
THE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
.............................................. 45
F
IGURE
32. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
PATH
WITHIN
A
GIVEN
CHANNEL
.................................................. 46
F
IGURE
33. T
HE
R
EMOTE
L
OOP
-B
ACK
PATH
,
WITHIN
A
GIVEN
CHANNEL
............................................................ 47
F
IGURE
34. T
HE
XRT73L04
EMPLOYING
THE
T
RANSMIT
D
RIVE
M
ONITOR
F
EATURES
........................................ 49
F
IGURE
35. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
D
ATA
S
TRUCTURE
.............................................................. 55
F
IGURE
36. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
.................................................. 56