XRT73L04
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. P1.0.5
á
PRELIMINARY
6
44
TxLEV0
I
Transmit Line Build-Out Enable/Disable Select - Channel 0:
This input pin permits the Transmit Line Build-Out circuit, within Channel
0, to be enabled or disabled. In E3 mode, this pin has no effect on the
transmit pulse shape.
Setting this pin to "High" disables the Line Build-Out circuit. In this
mode, Channel 0 outputs partially-shaped pulses onto the line via the
TTIP0 and TRing0 output pins.
Setting this pin to "Low" enables the Line Build-Out circuit within Channel
0. In this mode, Channel 0 outputs shaped pulses onto the line via the
TTIP0 and TRing0 output pins.
To comply with the Isolated DSX-3/STSX-1 Pulse Template Require-
ments per Bellcore GR-499-CORE or Bellcore GR-253-CORE:
1. Set this input pin to "1" if the cable length between the Cross-Connect
and the transmit output of Channel 0 is greater than 225 feet.
2. Set this input pin to "0" if the cable length between the Cross-Connect
and the transmit output of Channel 0 is less than 225 feet.
This pin is active only if the following two conditions are true:
a. The XRT73L04 is configured to operate in either the DS3 or SONET
STS-1 Modes.
b. The XRT73L04 is configured to operate in the Hardware Mode.
N
OTE
:
This pin to should be tied to GND if the XRT73L04 is going to be
operating in the HOST Mode, (internally pulled-down).
45
TAOS1
I
See description of pin 46, TAOS0
46
TAOS0
I
Transmit All Ones Select - Channel 0:
A "High" on this pin causes the Transmit Section, within Channel 0, to
generate and transmit a continuous AMI all “1’s" pattern onto the line.
The frequency of this "1’s" pattern is determined by TxClk0.
This input pin is ignored if the XRT73L04 is operating in the HOST Mode.
N
OTE
:
This pin should be tied to GND if the XRT73L04 is going to be
operating in the HOST Mode, (internally pulled-down).
47
TxAVDD0
****
Transmitter Analog Supply, 3.3V + 5% - Channel(n)
48
DMO0
O
Drive Monitor Output - Channel 0:
If no transmitted AMI signal is present on MTIP0 and MRing0 input pins
for 128±32 TxClk periods, then DMO0 toggles and remains "High" until
the next AMI signal is detected.
49
TxAGND0
****
Transmitter Analog Ground - Channel (n)
50
AGND0
****
Analog Ground Pin
51
RxDVDD1
****
Receiver Digital Supply 3.3V + 5% Channel (n)
52
HOST/(HW)
I
HOST-Hardware Mode Select:
This input pin is used to enable or disable the Microprocessor Serial
Interface (e.g., consisting of the SDI, SDO, SClk, and CS pins).
Setting this input pin "High" enables the Microprocessor Serial Interface
(e.g. configures the XRT73L04 to operate in the HOST Mode). In this
mode, configure the XRT73L04 via the Microprocessor Serial Interface.
When the XRT73L04 is operating in the HOST Mode, then it ignores the
states of many of the discrete input pins. Setting this input pin "Low" dis-
ables the Microprocessor Serial Interface (e.g., configures the
XRT73L04 to operate in the Hardware Mode). In this mode, many of the
external input control pins are functional. (Internally Pulled-up)
53
RxClk1
O
See description of pin 59, RxClk0
PIN #
NAME
TYPE
DESCRIPTION