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XRT73L04
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.0.5
45
4.0
The XRT73L04 supports equipment diagnostic activi-
ties by supporting the following Loop-Back modes
within each channel.
Analog Local Loop-Back.
Digital Local Loop-Back
Remote Loop-Back
N
OTE
:
In this data sheet we use the convention that Chan-
nel(n) refers to either channel 0, 1, 2 or 3. Similarly, specific
input and output pins uses this convention to denote which
channel it is associated with.
4.1
T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
When a given channel is configured to operate in the
Analog Local Loop-Back Mode, the channel ignores
any signals that are input to its RTIP(n) and RRing(n)
input pins. The Transmitting Terminal Equipment
transmits clock and data into this channel via the TP-
DIAGNOSTIC FEATURES OF THE XRT73L04
Data(n), TNData(n) and TxClk(n) input pins. This da-
ta is processed through the Transmit Clock Duty Cy-
cle Adjust PLL and the HDB3/B3ZS Encoder. Finally,
this data is output to the line via the TTIP(n) and
TRing(n) output pins. Additionally, this data which is
being output via the TTIP(n) and TRing(n) output pins
is also looped back into the Attenuator/Receive
Equalizer Block. Consequently, this data is pro-
cessed through the entire Receive Section of the
channel. After this post-Loop-Back data has been
processed through the Receive Section it outputs to
the Near-End Receiving Terminal Equipment via the
RPOS(n), RNEG(n) and RxClk(n) output pins.
Figure 31 illustrates the path that the data takes when
the channel is configured to operate in the Analog Lo-
cal Loop-Back Mode.
Configure a given channel to operate in the Analog
Local Loop-Back Mode by employing either one of
the following two steps
a. Operating in the HOST Mode
N
OTE
:
See Table 2 for a description of Command Regis-
ters and Addresses for the different channels.
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, write a “1" into the LLB(n) bit-
field and a "0" into the RLB(n) bit-field within Com-
mand Register CR4.
F
IGURE
31. A
CHANNEL
OPERATING
IN
THE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR(n)
SDI
SDO
SClk
CS/(SR/DR)
REGR
RTIP(n)
RRing(n)
REQEN(n)
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
Notes: 1. (n) = 0, 1, 2, or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
RLOL(n) EXClk(n)
Device
Monitor
MTIP(n)
MRing(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV(n)
TxOFF(n)
DMO(n)
TTIP(n)
TRing(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Analog Local
Loop-Back Path