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參數(shù)資料
| 型號： | XRT73L04 |
| 廠商： | Exar Corporation |
| 英文描述： | 4 Channel E3/DS3/STS-1 Line Interface Unit(4通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 4頻道E3/DS3/STS-1線路接口單元（4通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 31/62頁 |
| 文件大?。?/td> | 781K |
| 代理商： | XRT73L04 |
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XRT73L04
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.0.5
27
TxClk(n) is the clock signal that is of the selected data
rate frequency, E3 = 34.368 MHz, DS3 = 44.736 MHz
and STS-1 = 51.84 MHz. If the Transmit Section
samples a "1" on the TPData(n) input pin, then the
Transmit Section of the device ultimately generates a
positive polarity pulse via the TTIP(n) and TRing(n)
output pins across a 1:1 transformer. Conversely, if
the Transmit Section samples a "1" on the TNData(n)
input pin, then the Transmit Section of the device ulti-
mately generates a negative polarity pulse via the
TTIP(n) and TRing(n) output pins across a 1:1 trans-
former.
2.1.2
Accepting Single-Rail Data from the Ter-
minal Equipment
To transmit data in a Single-Rail data from the Termi-
nal Equipment, configure the XRT73L04 in the HOST
Mode.
To Configure Channel(n) to accept Single-Rail Da-
ta from the Terminal Equipment:
Write a "1" into the (SR/DR)_(n) bit-field, within Com-
mand Register CR3-(n) shown below. (Please refer
toTable 2 for the Address of the individual (n) channel.
The Transmit Section (of each channel) samples this
input pin on the falling edge of the TxClk(n) clock sig-
nal and encodes this data into the appropriate bipolar
line signal across the TTIP(n) and TRing(n) output
pins.
N
OTES
:
1. In this mode, the Transmit Logic Block ignores the
TNData(n) input pin.
2. If the Transmit Section of a given channel is config-
ured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 13 Illustrates the behavior of the TPData(n)
and TxClk(n) signals when the Transmit Logic Block
has been configured to accept Single-Rail data from
the Terminal Equipment.
2.2
T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IR
-
CUITRY
The on-chip Pulse-Shaping circuitry within the Trans-
mit Section of each Channel in the XRT73L04 gener-
F
IGURE
12. T
HE
XRT73L04 S
AMPLES
THE
DATA
ON
THE
TPD
ATA
AND
TND
ATA
INPUT
PINS
TxClk
TPData
TNData
Data 1 1 0
COMMAND REGISTER CR3-(N)
D4
D3
D2
D1
D0
(SR/
DR)_(n)
LOSMUT(n) RxOFF RxClk(n)INV Reserved
1
x
x
x
x
F
IGURE
13. T
HE
B
EHAVIOR
OF
THE
TPD
ATA
AND
T
X
C
LK
I
NPUT
S
GNALS
,
WHILE
THE
T
RANSMIT
L
OGIC
B
LOCK
IS
A
CCEPTING
S
INGLE
-R
AIL
D
ATA
FROM
THE
T
ERMINAL
E
QUIPMENT
TxClk
TPData
Data 1 1 0
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| XRT73L06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L06IB | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC00A | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC00AIV | E3/DS3/STS-1 LINE INTERFACE UNIT |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L04A | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04B | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04BES | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L04BIV | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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