參數(shù)資料
型號: XRT75VL00IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP52
封裝: 10 X 10 MM, TQFP-52
文件頁數(shù): 35/50頁
文件大小: 268K
代理商: XRT75VL00IV
XRT75VL00
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
33
6.0
There are three fundamental parameters that describe circuit performance relative to jitter:
Jitter Tolerance (Receiver)
Jitter Transfer (Receiver/Transmitter)
Jitter Generation
6.1
J
ITTER
T
OLERANCE
- R
ECEIVER
:
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence.
JITTER:
Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as
a combination of points.Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter
frequency.
6.1.1
DS3/STS-1 Jitter Tolerance Requirements:
Bellcore GR-499 CORE, Issue 1, December 1995 specifies the minimum requirement of jitter tolerance for
Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22
shows the jitter tolerance curve as per GR-499 specification along with the measured performance for the
device.
F
IGURE
21. J
ITTER
T
OLERANCE
M
EASUREMENTS
Synthesizer
FREQ
Synthesizer
Pattern
Generator
XRT75VL00
DUT
XRT75VL00
Error
Detector
Modulation
Freq.
Data
Clock
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