參數(shù)資料
型號： XRT75VL00IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP52
封裝： 10 X 10 MM, TQFP-52
文件頁數(shù)： 4/50頁
文件大小： 268K
代理商： XRT75VL00IV
XRT75VL00
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
F
EATURES
.....................................................................................................................................................1
A
PPLICATIONS
................................................................................................................................................1
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
........................................................................................................2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................................2
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75VL00............................................................................................................................ 2
J
ITTER
A
TTENUATORS
....................................................................................................................................3
F
IGURE
2. P
IN
O
UT
OF
THE
XRT75VL00 ......................................................................................................................................... 3
ORDERING INFORMATION.....................................................................................................................3
TABLE OF CONTENTS I
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................4
T
RANSMIT
I
NTERFACE
.....................................................................................................................................4
R
ECEIVE
I
NTERFACE
.......................................................................................................................................6
C
LOCK
I
NTERFACE
.........................................................................................................................................8
O
PERATING
M
ODE
S
ELEC
T ............................................................................................................................9
C
ONTROL
AND
A
LARM
I
NTERFACE
...................................................................................................................9
M
ICROPROCESSOR
S
ERIAL
INTERFACE - (HOST MODE).........................................................................11
...................................................................................................................................................................13
J
ITTER
A
TTENUATOR
INTERFACE
...................................................................................................................13
A
NALOG
P
OWER
AND
G
ROUND
.....................................................................................................................14
D
IGITAL
P
OWER
AND
G
ROUND
.....................................................................................................................14
1.0 ELECTRICAL CHARACTERISTICS ....................................................................................................15
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
......................................................................................................................................... 15
T
ABLE
2: DC E
LECTRICAL
C
HARACTERISTICS
:................................................................................................................................ 15
2.0 TIMING CHARACTERISTICS ..............................................................................................................16
F
IGURE
3. T
YPICAL
INTERFACE
BETWEEN
TERMINAL
EQUIPMENT
AND
THE
XRT75VL00 (
DUAL
-
RAIL
DATA
)........................................ 16
F
IGURE
4. T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
.......................................................................................................................... 16
F
IGURE
5. R
ECEIVER
D
ATA
OUTPUT
AND
CODE
VIOLATION
TIMING
................................................................................................... 17
F
IGURE
6. T
RANSMIT
P
ULSE
A
MPLITUDE
TEST
CIRCUIT
FOR
E3, DS3
AND
STS-1 R
ATES
................................................................. 17
3.0 LINE SIDE CHARACTERISTICS: ........................................................................................................18
3.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 18
F
IGURE
7. P
ULSE
M
ASK
FOR
E3 (34.368
MBITS
/
S
)
INTERFACE
AS
PER
ITU
-
T
G.703......................................................................... 18
T
ABLE
3: E3 T
RANSMITTER
AND
RECEIVER
LINE
SIDE
SPECIFICATIONS
(T
A
= 250C
AND
VDD = 3.3 V ± 5%) ................................... 18
F
IGURE
8. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE
FOR
SONET STS-1 A
PPLICATIONS
............................. 19
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
..................................................................................................................................... 19
T
ABLE
5: STS-1 T
RANSMITTER
AND
R
ECEIVER
L
INE
S
IDE
S
PECIFICATIONS
(TA = 250C
AND
VDD =3.3V ± 5%) ............................ 20
F
IGURE
9. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE
FOR
DS3
AS
PER
B
ELLCORE
GR-499..................................................................... 20
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................ 21
T
ABLE
7: DS3 T
RANSMITTER
AND
R
ECEIVER
L
INE
S
IDE
S
PECIFICATIONS
(T
A
= 250C
AND
VDD = 3.3V ± 5%)................................ 21
F
IGURE
10. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
S
TRUCTURE
...................................................................................................... 22
F
IGURE
11. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 22
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND
LOAD
= 10
P
F).................................. 23
4.0 THE TRANSMITTER SECTION: .........................................................................................................24
4.1 TRANSMIT CLOCK: ....................................................................................................................................... 24
4.2 B3ZS/HDB3 ENCODER: ................................................................................................................................. 24
4.2.1 B3ZS ENCODING: ...................................................................................................................................................... 24
F
IGURE
12. S
INGLE
-R
AIL
OR
NRZ D
ATA
F
ORMAT
(E
NCODER
AND
D
ECODER
ARE
E
NABLED
)............................................................ 24
F
IGURE
13. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER
AND
DECODER
ARE
DISABLED
)............................................................................. 24
4.2.2 HDB3 ENCODING:...................................................................................................................................................... 25
4.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 25
F
IGURE
14. B3ZS E
NCODING
F
ORMAT
........................................................................................................................................... 25
F
IGURE
15. HDB3 E
NCODING
F
ORMAT
.......................................................................................................................................... 25
4.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT:................................................................................. 26
4.3.2 INTERFACING TO THE LINE:.................................................................................................................................... 26
4.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 26
F
IGURE
16. T
RANSMIT
D
RIVER
M
ONITOR
SET
-
UP
............................................................................................................................ 26
4.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 27
5.0 THE RECEIVER SECTION: .................................................................................................................28
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75VL00IV-F 功能描述:外圍驅(qū)動器與原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75VL00IVTR 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75VL00IVTR-F 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT79L71 制造商:EXAR 制造商全稱:EXAR 功能描述:1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC -
XRT79L71_07 制造商:EXAR 制造商全稱:EXAR 功能描述:1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
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