參數(shù)資料
型號: XRT75VL00IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP52
封裝: 10 X 10 MM, TQFP-52
文件頁數(shù): 43/50頁
文件大?。?/td> 268K
代理商: XRT75VL00IV
XRT75VL00
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
41
0x05
R/W
D0
REQEN
Setting this bit to “1” enables the Receive Equalizer .
N
OTE
:
See section 2.01 for detailed description.
0
D1
RxMON
Writing a “1” to this bit configures the Receiver into
monitoring mode. In this mode, the Receiver can
monitor a signal at the RTIP/RRing pins that be atten-
uated up to 20dB flat loss.
0
D2
LOSMUT
Writing a “1” to this bit causes the RPOS/RNEG out-
puts to be grounded while the LOS condition is
declared.
N
OTE
:
If this bit has ben set, it will remain set evan
after LOS condition is cleared.
0
D3
RxClkINV
Writing a “1” to this bit configures the Receiver to out-
put RPOS/RNEG data on the falling edge of RxClk.
0
D4
ALOSDIS
Writing a “1” to this bit disables the ALOS detector.
0
D5
DLOSDIS
Writing a “1” to this bit disables the DLOS detector.
0
0x06
R/W
D0
SR/DR
Writing a “1” to this bit configures the Receiver and
Transmitter into Single-Rail (NRZ) mode.
0
D1
STS-1/DS3
Writing a “1” to this bit configures the channel 0 into
STS-1 mode.
N
OTE
:
This bit field is ignored if the chip is configured
to operate in E3 mode.
0
D2
E3
Writing a “1” to this bit configures the chip in E3
mode.
0
D3
LLB
Writing a “1” to this bit configures the chip in Local
Loopback mode.
0
D4
RLB
Writing a “1” to this bit configures the chip in Remote
Loopback mode.
0
D5
PRBSEN
Writing a “1” to this bit enables the PRBS generator/
detector.PRBS generator generate and detect either
2
15
-1 (DS3 or STS-1) or 2
23
-1 (for E3).
The pattern generated and detected are unframed
pattern.
0
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
A
DDRESS
(H
EX
)
T
YPE
B
IT
L
OCATION
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
(B
IN
)
RLB
0
0
Loopback Mode
Normal Operation
Analog Local
LLB
0
1
1
1
Remote
Digital
0
1
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