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參數(shù)資料
| 型號： | XRT75VL00IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP52 |
| 封裝： | 10 X 10 MM, TQFP-52 |
| 文件頁數(shù)： | 6/50頁 |
| 文件大?。?/td> | 268K |
| 代理商： | XRT75VL00IV |
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XRT75VL00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.3
4
PIN DESCRIPTIONS (
BY FUNCTION
)
TRANSMIT INTERFACE
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
4
TxON
I
Transmitter ON Input
Setting this input pin "High" turns on the Transmitter.
N
OTES
:
1.
Even when the XRT75VL00 is configured in HOST mode, this pin still
controls the TTIP and TRING outputs
2.
When the Transmitter is turned off either in Host or Hardware
mode,the TTIP and TRING outputs are Tri-stated.
3.
This pin is internally pulled down
46
TxClk
I
Transmit Clock Input for TPData and TNData
The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm.
The duty cycle can be 30%-70%.
The XRT75VL00 samples the TPData and TNData pins on the falling or rising
edge of TxClk signal based on the status of TxClkINV pin (in Hardware mode)
or the status of the bit in the Channel Register (in HOST mode).
26
TxClkINV/
SClk
I
Transmit Clock Invert or Serial Clock Input:
Function of this depends on whether the XRT75VL00 is configured to operate in
Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Transmitter to
sample the TPData and TNData data on the rising edge of the TxClk.
N
OTE
:
If the XRT75VL00 is configured in HOST mode, this pin functions as
SClk input pin (please refer to the pin description for Microprocessor
interface).
48
TNData
I
Transmit Negative Data Input
If the XRT75VL00 is configured in Dual-rail mode, this pin is sampled on the
falling or rising edge of TxClk based on the status of the TClkINV pin (in Hard-
ware mode) or the status of the control bit in the Channel Register (in HOST
mode).
N
OTES
:
1.
This input pin is ignored and should be tied to GND if the Transmitter
Section is configured to accept Single-Rail data from the Terminal
Equipment.
47
TPData
I
Transmit Positive Data Input
The XRT75VL00 samples this pin on the falling or rising edge of TxClk based
on the status of the TClkINV pin (in Hardware mode) or the status of the control
bit in the Channel Register (in HOST mode).
50
TTIP
O
Transmit TTIP Output
The XRT75VL00 uses this pin along with TRING to transmit a bipolar signal to
the line using a 1:1 transformer.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75VL00IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75VL00IVTR | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75VL00IVTR-F | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT79L71 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - |
| XRT79L71_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE |
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