參數(shù)資料
型號: XRT75VL00IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP52
封裝: 10 X 10 MM, TQFP-52
文件頁數(shù): 47/50頁
文件大小: 268K
代理商: XRT75VL00IV
XRT75VL00
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
45
N
OTES
:
1.
2.
In the Analog loopback mode, data is also output via TTIP and TRING pins.
Signals on the RTIP and RRING pins are ignored during analog loopback.
8.2.2
The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback
is selected, the transmit clock (TxClk) and transmit data inputs (TPDATA & TNDATA) are looped back and
output onto the RxClk, RPOS and RNEG pins as shown in Figure 27. The data presented on TxClk, TPDATA
and TNDATA are not output on the TTIP and TRING pins.This provides the capability to configure the
protection card (in redundancy applications) in Digital Loopback mode without affecting the traffic on the
primary card.
DIGITAL LOOPBACK:
N
OTE
:
Signals on the RTIP and RRING pins are ignored during digital loopback.
F
IGURE
26. A
NALOG
L
OOPBACK
F
IGURE
27. D
IGITAL
L
OOPBACK
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
1
ENCODER
HDB3/B3ZS
1
DECODER
J
A
J
A
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1
if enabled
2
if enabled and selected in either Receive or Transmit path
Tx
Rx
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
ENCODER
1
HDB3/B3ZS
DECODER
1
J
A
J
A
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1
if enabled
2
if enabled and selected in either Receive or Transmit path
Tx
Rx
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