參數(shù)資料
型號(hào): XRT75VL00IV
廠(chǎng)商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP52
封裝: 10 X 10 MM, TQFP-52
文件頁(yè)數(shù): 8/50頁(yè)
文件大小: 268K
代理商: XRT75VL00IV
XRT75VL00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.3
6
RECEIVE INTERFACE
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
25
RxON/
SDI
I
Receiver Turn ON Input or Serial Data Input:
Function of this pin depends on whether the XRT75VL00 is configured to oper-
ate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” turns on and enables the
Receiver..
N
OTES
:
1.
If the XRT75VL00 is configured in HOST mode, this pin functions as
SDI input pin (please refer to the pin description for Microprocessor
Interface)
2.
This pin is internally pulled down.
23
REQEN
I
Receive Equalization Enable Input
Setting this input pin "High" enables the Internal Receive Equalizer. Setting this
pin "Low" disables the Internal Receive Equalizer.
N
OTES
:
1.
This input pin is ignored and may be connected to GND if the
XRT75VL00 is operating in the HOST Mode
2.
This pin is internally pulled down.
36
RxClk
O
Receive Clock Output
The Recovered Clock signal from the incoming line signal is output through this
pin.By default, the Receiver Section outputs data via RPOS and RNEG pins on
the rising edge of this clock signal.
Configure the Receiver Section to update data on the RPOS and RNEG pins on
the falling edge of RxClk by doing the following:
a)
Operating in Hardware mode
, pull the RxClkINV pin to “High”.
b)
Operating in Host mode
, write a “1” to RxClkINV bit field within the Receive
Control Register.
24
RxClkINV/
CS
I
RxClk INVERT or Chip Select
:
Function of this pin depends on whether the XRT75VL00 is configured to oper-
ate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Receiver Sec-
tion to invert the RxClk output signals and outputs the recovered data via
RPOS and RNEG on the falling edge of RxClk.
N
OTE
:
If the XRT75VL00 is configured in HOST mode, this pin functions as CS
input pin (please refer to the pin description for Microprocessor
Interface).
38
RPOS
O
Receive Positive Data Output
This output pin pulses “High" whenever the XRT75VL00 has received a Posi-
tive Polarity pulse in the incoming line signal at the RTIP/RRing inputs.
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