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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PRELIMINARY
XRT79L71
REV. P1.0.3
10
363
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
T
EST
C
ELL
H
EADER
B
YTE
- B
YTE
4 (A
DDRESS
= 0
X
1F23)
364
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM C
ELL
C
OUNTER
- B
YTE
3 (A
DDRESS
= 0
X
1F28)364
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM C
ELL
C
OUNTER
- B
YTE
2 (A
DDRESS
= 0
X
1F29)365
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM C
ELL
C
OUNTER
- B
YTE
1 (A
DDRESS
= 0
X
1F2A)365
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM C
ELL
C
OUNTER
- B
YTE
0 (A
DDRESS
= 0
X
1F2B)366
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
D
ISCARDED
ATM C
ELL
C
OUNT
- B
YTE
3 (A
DDRESS
= 0
X
1F2C)
367
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
D
ISCARDED
ATM C
ELL
C
OUNT
- B
YTE
2 (A
DDRESS
= 0
X
1F2D)
367
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
D
ISCARDED
ATM C
ELL
C
OUNT
- B
YTE
1 (A
DDRESS
= 0
X
1F2E)
368
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
D
ISCARDED
ATM C
ELL
C
OUNT
- B
YTE
0 (A
DDRESS
= 0
X
1F2F)
368
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM HEC B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
3 (A
DDRESS
= 0
X
1F30) ................................................................................................................................................369
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM HEC B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
2 (A
DDRESS
= 0
X
1F31) ................................................................................................................................................369
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM HEC B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
= 0
X
1F32) ................................................................................................................................................370
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM HEC B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
0 (A
DDRESS
= 0
X
1F33) ................................................................................................................................................370
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
UTOPIA P
ARITY
E
RROR
C
OUNT
R
EGISTER
- B
YTE
3 (A
D
-
DRESS
= 0
X
1F34) .....................................................................................................................................371
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
UTOPIA P
ARITY
E
RROR
C
OUNT
R
EGISTER
- B
YTE
2 (A
D
-
DRESS
= 0
X
1F35) .....................................................................................................................................371
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
UTOPIA P
ARITY
E
RROR
C
OUNT
R
EGISTER
- B
YTE
1 (A
D
-
DRESS
= 0
X
1F36) .....................................................................................................................................372
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
UTOPIA P
ARITY
E
RROR
C
OUNT
R
EGISTER
- B
YTE
0 (A
D
-
DRESS
= 0
X
1F37) .....................................................................................................................................372
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
C
ONTROL
- F
ILTER
0 (A
DDRESS
= 0
X
1F43)
373
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - P
ATTERN
R
EGISTER
- H
EADER
B
YTE
1 (A
DDRESS
= 0
X
1F44).............................................................................................................................375
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - P
ATTERN
R
EGISTER
- H
EADER
B
YTE
2 (A
DDRESS
= 0
X
1F45).............................................................................................................................376
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - P
ATTERN
R
EGISTER
- H
EADER
B
YTE
3 (A
DDRESS
= 0
X
1F46).............................................................................................................................377
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - P
ATTERN
R
EGISTER
- H
EADER
B
YTE
4 (A
DDRESS
= 0
X
1F47).............................................................................................................................378
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - C
HECK
R
EGISTER
- B
YTE
1 (A
DDRESS
= 0
X
1F48) ................................................................................................................................................379
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - C
HECK
R
EGISTER
- B
YTE
2 (A
DDRESS
= 0
X
1F49) ................................................................................................................................................380
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - C
HECK
R
EGISTER
- B
YTE
3 (A
DDRESS
= 0
X
1F4A)................................................................................................................................................381
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - C
HECK
R
EGISTER
- B
YTE
4 (A
DDRESS
= 0
X
1F4B)................................................................................................................................................382
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - F
ILTERED
C
ELL
C
OUNT
- B
YTE
3
(A
DDRESS
= 0
X
1F4C)...............................................................................................................................383
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - F
ILTERED
C
ELL
C
OUNT
- B
YTE
2
(A
DDRESS
= 0
X
1F4D)...............................................................................................................................384
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
U
SER
C
ELL
F
ILTER
# 0 - F
ILTERED
C
ELL
C
OUNT
- B
YTE
1
(A
DDRESS
= 0
X
1F4E) ...............................................................................................................................385