XRT79L71
REV. P1.0.3
PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
á
126
4
Change of Idle Condition
Interrupt Status
RUR
Change in Idle Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
"Change in Idle Condition" interrupt has occurred since the last
read of this register.
0 - The "Change in Idle Condition" Interrupt has not occurred
since the last read of this register.
1 - The "Change in Idle Condition" Interrupt has occurred since
the last read of this register.
N
OTE
:
This bit-field is ignored if the Frame Synchronizer block is
by-passed.
3
Change of FERF Condi-
tion Interrupt Status
RUR
Change in FERF Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
"Change in FERF Condition" Interrupt has occurred since the
last read of this register.
0 - The "Change in FERF Condition" Interrupt has not occurred
since the last read of this register.
1 - The "Change in FERF Condition" Interrupt has occurred
since the last read of this register.
N
OTE
:
This bit-field is ignored if the Frame Synchronizer block is
by-passed.
2
Change of AIC State
Interrupt Status
RUR
Change in AIC State Interrupt Status:
This RESET-upon-READ register bit indicates whether or not the
"Change in AIC State" interrupt has occurred since the last read
of this register.
0 - The "Change in AIC State" Interrupt has not occurred since
the last read of this register.
1 - The "Change in AIC State" Interrupt has occurred since the
last read of this register.
N
OTE
:
This bit-field is ignored if the Frame Synchronizer block is
by-passed.
1
Change of OOF Condi-
tion Interrupt Status
RUR
Change in OOF Condition Interrupt Status:
This RESET-upon-READ register indicates whether or not the
"Change in OOF Condition" Interrupt has occurred since the last
read of this register.
0 - The "Change in OOF Condition" Interrupt has not occurred
since the last read of this register.
1 - The "Change in OOF Condition" Interrupt has occurred since
the last read of this register.
N
OTE
:
This bit-field is ignored if the Frame Synchronizer block is
by-passed.
0
Detection of P-Bit Error
Interrupt Status
RUR
Detection of P-Bit Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Detection of CP-Bit Error" Interrupt has occurred since the last
read of this register.
0 - The "Detection of CP-Bit Error" Interrupt has not occurred
since the last read of this register.
1 - The "Detection of CP-Bit Error" Interrupt has occurred since
the last read of this register.
N
OTE
:
This bit-field is ignored if the Frame Synchronizer block is
by-passed.
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION