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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PRELIMINARY
XRT79L71
REV. P1.0.3
17
D8
TxNib_1/
Tx8KREF/
TxHDLCDat_1
I
Transmit Nibble Input Interface - Bit 1/Transmit PLCP Framing 8kHz Refer-
ence Input/Transmit HDLC Controller Data Bus - Bit 1 Input:
The function of this input pin depends upon whether the XRT79L71 is configured
to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Controller
Mode, or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_1:
If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this
input pin will function as the bit 1 input to the Transmit Nibble-Parallel input inter-
face. The Transmit Payload Data Input Interface block will sample this signal
(along with TxNib_0, TxNib_2 and TxNib_3) upon the falling edge of TxNibClk.
N
OTE
:
This input pin is inactive if the XRT79L71 is configured to operate in the
Serial Mode.
ATM/PLCP Mode - Tx8KREF:
If the XRT79L71 is configured to operate in the ATM/PLCP Mode, then the Trans-
mit PLCP Processor can be configured to synchronize its PLCP frame genera-
tion to this input clock signal. The Transmit PLCP Processor will also use this
input signal to compute the nibble-trailer stuff opportunities.
N
OTE
:
This input pin is inactive if the use has configured the XRT79L71 to
operate in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_1:
If the XRT79L71 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. This input pin will function as Bit 1
within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signal.
A9
TxNib_0/
TxGFC/
TxHDLCDat_0
I
Transmit Nibble Interface - Bit 0/Transmit GFC Input pin/Transmit HDLC
Controller Data Bus - Bit 0 Input:
The function of this input pin depends upon whether the XRT79L71 is configured
to operate in the Clear-Channel Framer Mode, the High Speed HDLC Controller
Mode or in the ATM Mode.
Clear-Channel Framer Mode - TxNib_0:
If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this
input pin will function as the bit 0 (LSB) input to the Transmit Nibble-Parallel input
interface. The Transmit Payload Data Input Interface block will sample this signal
(along with TxNib_1 through TxNib_3) upon the falling edge of TxNibClk.
N
OTE
:
This input pin is inactive if the XRT79L71 is configured to operate in the
Serial Mode.
ATM Mode - TxGFC:
This signal, along with TxGFCMSB, and TxGFCClk combine to function as the
Transmit GFC Nibble Field serial input port. The user will specify the value of the
GFC field, within a given ATM cell, by serially transmitting its four bit-value into
this input pin. Each of these four bits will be clocked into the port upon the rising
edge of the TxGFCClk output signal.
High-Speed HDLC Controller Mode - TxHDLCDat_0:
If the XRT79L71 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. This input pin will function as Bit 0
(the LSB) within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signal.
P
IN
#
N
AME
TYPE
D
ESCRIPTION