XRT79L71
REV. P1.0.3
PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
á
32
L2
RxPERR
O
Receive POS-PHY Interface - Error Indicator:
This output pin indicates whether or not the Receive POS-PHY Interface has
detected an error in the inbound PPP Packet.
This output pin toggles "High" if the Receive Section of the XRT79L71 detects
an FCS Error, an ABORT sequence or a Runt Packet.
N
OTE
:
This output pin is only valid if the XRT79L71 has been configured to
operate in the PPP Mode.
K4
RxTSX/
RxPSOF
O
Receive - Start of Transfer/Receive - Start of PPP Packet in Chunk Mode:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the Packet Mode or Cell-Chunk Mode.
Packet Mode - RxTSX:
The XRT79L71 pulses this output pin "High" when an inband port address is
present on the RxPData[7:0] bus.
When this output pin is "High", the value of RxPData[7:0] is the address value of
the RxFIFO to be selected. Subsequent read operations, from RxPData[15:0]
will be from the RxFIFO corresponding to this inband address.
Chunk Mode - RxPSOF:
The XRT79L71 pulses this output pin "High" in order to indicate that the first
byte (or word) of a given Packet is placed on the RxPData[15:0] pins.
N
OTE
:
This output pin is only active if the XRT79L71 has been configured to
operate in the PPP Mode.
H4
RxUEN/
RxPEN
I
Receive UTOPIA Interface - Output Enable/Receive POS-PHY Interface -
Output Enable:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the ATM UNI or PPP mode.
ATM UNI Mode - RxUEN:
This active-low input signal is used to control the drivers of the Receive UTOPIA
Data Bus. When this signal is "High" (negated) then the Receive UTOPIA Data
Bus is tri-stated. When this signal is asserted, then the contents of the byte or
word that is at the front of the RxFIFO will be popped and placed on the Receive
UTOPIA Data bus on the very next rising edge of RxUClk.
PPP Mode - RxPEN:
This active-low input signal is used to control the drivers of the Receive POS-
PHY Data Bus. When this signal is "High" (negated) then the Receive POS-
PHY Data Bus is tri-stated. When this signal is asserted, then the contents of
the byte or word that is at the front of the RxFIFO will be popped and placed on
the Receive POS-PHY Data bus on the very next rising edge of RxPClk.
H2
RxUSoC/
RxPSOP
O
Receive UTOPIA Interface - Start of Cell Indicator/Receive POS-PHY Inter-
face - Start of Packet Indicator:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the ATM UNI or in the PPP Mode.
ATM UNI Mode - RxUSoC:
This output pin allows the ATM Layer Processor to determine the boundaries of
the ATM cells that are output via the Receive UTOPIA Data bus. The Receive
UTOPIA Interface block will assert this signal when the first byte (or word) of a
new cell is present on the Receive UTOPIA Data Bus; RxUData[15:0].
PPP Mode - RxPSOP:
This output pin allows the Link Layer Processor to determine the boundaries of
the PPP packets that are output via the Receive POS-PHY Data Bus. The
Receive POS-PHY Interface block will assert this signal when the first byte (or
word) of a new packet is present on the Receive POS-PHY Data Bus, RxP-
Data[15:0].
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IN
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AME
TYPE
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ESCRIPTION