XRT79L71
REV. P1.0.3
PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
á
1
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
GENERAL
F
EATURES
:......................................................................................................................................1
Line Interface Unit .......................................................................................................................................................1
DS3/E3 Framer............................................................................................................................................................1
ATM/PPP PROTOCOL PROCESSOR........................................................................................................................1
Transmit Cell Processing.............................................................................................................................................1
Receive Cell Processing..............................................................................................................................................2
Transmit Packet Processing........................................................................................................................................2
Receive Packet Processing.........................................................................................................................................2
Utopia/ System Interface .............................................................................................................................................2
Serial Interface ............................................................................................................................................................2
APPLICATIONS...........................................................................................................................................2
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT79L71 ............................................................................................................................... 2
P
RODUCT
O
RDERING
I
NFORMATION
................................................................................................................2
T
ABLE
1: P
IN
O
UT
OF
THE
XRT79L71 (TOP VIEW) ........................................................................................................................ 3
T
ABLE
OF
C
ONTENTS
...........................................................................................................1
P
IN
D
ESCRIPTIONS
.........................................................................................................................................4
M
ICROPROCESSOR
I
NTERFACE
.......................................................................................................................4
T
EST
AND
D
IAGNOSTIC
...................................................................................................................................7
G
ENERAL
P
URPOSE
I
NPUT
AND
O
UTPUT
P
INS
.................................................................................................8
T
RANSMIT
S
YSTEM
S
IDE
I
NTERFACE
P
INS
.......................................................................................................8
R
ECEIVE
S
YSTEM
S
IDE
I
NTERFACE
P
INS
.......................................................................................................23
T
RANSMIT
L
INE
S
IDE
S
IGNALS
......................................................................................................................35
R
ECEIVE
L
INE
S
IDE
S
IGNALS
........................................................................................................................36
VDD P
INS
...................................................................................................................................................37
GND P
INS
...................................................................................................................................................38
N
OT
C
ONNECTED
P
INS
.................................................................................................................................38
ELECTRICAL CHARACTERISTICS................................................................................39
AC ELECTRICAL CHARACTERISTIC INFORMATION..................................................39
MICROPROCESSOR INTERFACE TIMING
FOR
R
EVISION
A S
ILICON
......................................................39
MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS INTEL MODE....................................................39
T
ABLE
2: DC ELECTRICAL CHARACTERISTICSS..................................................................................................................... 39
Applies to all TTL-Level Input and CMOS Level Output pins - Ambient Temperature = 25°C..................................39
F
IGURE
2. A
SYNCHRONUS
M
ODE
1 - I
NTEL
TYPE
P
ROGRAMMED
I/O T
IMING
(W
RITE
C
YCLE
)............................................................ 39
F
IGURE
3. A
SYNCHRONUS
M
ODE
1 - I
NTEL
TYPE
P
ROGRAMMED
I/O T
IMING
(R
EAD
C
YCLE
) ............................................................. 40
T
ABLE
3: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN
CONFIGURED
TO
OPERATE
IN
THE
I
NTEL
A
SYNCHRONOUS
M
ODE
............................................................................................................................................................................ 40
MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K)
MODE................................................................................................................................41
F
IGURE
4. A
SYNCHRONUS
M
ODE
2 - M
OTOROLA
68K P
ROGRAMMED
I/O T
IMING
(W
RITE
C
YCLE
) .................................................... 41
F
IGURE
5. A
SYNCHRONUS
M
ODE
2 - M
OTOROLA
68 P
ROGRAMMED
I/O T
IMING
(R
EAD
C
YCLE
)........................................................ 41
MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE42
T
ABLE
4: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
WHEN
CONFIGURED
TO
OPERATE
IN
THE
M
OTOROLA
(68K) A
SYN
-
CHRONOUS
M
ODE
........................................................................................................................................................... 42
F
IGURE
6. S
YNCHRONOUS
M
ODE
3 - IBM P
OWER
PC 403 I
NTERFACE
TIMING
(W
RITE
C
YCLE
)......................................................... 42
F
IGURE
7. S
YNCHRONOUS
M
ODE
3 - IBM P
OWER
PC 403 I
NTERFACE
TIMING
(R
EAD
C
YCLE
)........................................................... 43
T
ABLE
5: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN
CONFIGURED
TO
OPERATE
IN
THE
IBM P
OWER
PC403
M
ODE
............................................................................................................................................................................ 43
MICROPROCESSOR INTERFACE TIMING - IDT3051/52 MODE ..................................44
F
IGURE
8. S
YNCHRONOUS
M
ODE
4 - IDT 3051/52 I
NTERFACE
TIMING
(W
RITE
C
YCLE
).................................................................... 44
F
IGURE
9. S
YNCHRONOUS
M
ODE
4 - IDT 3051/52 I
NTERFACE
TIMING
(R
EAD
C
YCLE
)...................................................................... 45
T
ABLE
6: T
IMING
I
NFORMATION
FOR
THE
M
ICROPROCESSOR
I
NTERFACE
,
WHEN
CONFIGURED
TO
OPERATE
IN
THE
IBM P
OWER
PC403
M
ODE
............................................................................................................................................................................ 45
DS3/E3 LIU INTERFACE - LINE SIDE ELECTRICAL CHARACTERISTIC INFORMATION
46