
XRT79L71
REV. P1.0.3
PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
á
350
TRANSMIT ATM CELL PROCESSOR BLOCK - TRANSMIT ATM INTERRUPT STATUS REGISTER
(ADDRESS = 0X1F0B)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Transmit Cell
Extraction
Interrupt Sta-
tus
Transmit Cell
Insertion
Interrupt Sta-
tus
Transmit Cell
Extraction
Memory
Overflow
Interrupt Sta-
tus
Transmit Cell
Insertion
Memory
Overflow
Interrupt Sta-
tus
Detection of
HEC Byte
Error Inter-
rupt Status
Detection of
Transmit
UTOPIA Par-
ity Error Inter-
rupt Status
R/O
R/O
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7 - 6
Unused
R/O
5
Transmit Cell Extraction
Interrupt Status
RUR
Transmit Cell Extraction Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Transmit Cell Extraction" interrupt has occurred since the last read
of this register.The Transmit ATM Cell Processor block will generate
the "Transmit Cell Extraction" Interrupt anytime it receives an incom-
ing ATM cell (from the TxFIFO) and loads an ATM cell into the
"Extraction Memory" Buffer.
0 - Indicates that the "Transmit Cell Extraction" Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the "Transmit Cell Extraction" Interrupt has
occurred since the last read of this register.
4
Transmit Cell Insertion
Interrupt Status
RUR
Transmit Cell Insertion Interrupt:
This RESET-upon-READ bit-field indicates whether or not the
"Transmit Cell Insertion" interrupt has occurred since the last read of
this register.
The Transmit ATM Cell Processor block will generate the "Transmit
Cell Insertion" Interrupt anytime a cell (residing in the Transmit Cell
Insertion Buffer) is read out of the "Transmit Cell Insertion Buffer"
and is loaded into the outbound ATM cell traffic.
0 - Indicates that the "Transmit Cell Insertion" Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the "Transmit Cell Insertion" Interrupt has occurred
since the last read of this register.
3
Transmit Cell Extraction
Memory Overflow Inter-
rupt Status
RUR
Transmit Cell Extraction Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Transmit Cell Extraction Memory Overflow" Interrupt has occurred
since the last read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime an overflow event has occurred in the "Transmit Cell Extrac-
tion Memory" Buffer.
0 - Indicates that the Transmit ATM Cell Processor block has NOT
declared the "Transmit Cell Extraction Memory Overflow" Interrupt
since the last read of this register.
1 - Indicates that the Transmit ATM Cell Processor block has
declared the "Transmit Cell Extraction Memory Overflow" interrupt
since the last read of this register.